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NXP Semiconductors
Name
TIMERS_WDOG_INT_SET_STATUS_REG
TIMERS_INT_CLR_ENABLE_REG
TIMERS_INT_SET_ENABLE_REG
TIMERS_INT_STATUS_REG
TIMERS_INT_ENABLE_REG
TIMERS_INT_CLR_STATUS_REG
TIMERS_INT_SET_STATUS_REG
RESERVED
11.4.2 Register description
Table 150. TIMERS_TIMER0_CONTROL_REG (address offset 0x0000)
Bit
Symbol
31:1
RESERVED
0
TIMER0_MODE
Table 151. TIMERS_TIMER0_TIMEOUT_REG (address offset 0x0004)
Bit
Symbol
31:12
RESERVED
11:0
TIMER0_TIMEOUT
Table 152. TIMERS_TIMER0_COUNT_REG (address offset 0x0008)
Bit
Symbol
31:12
RESERVED
11:0
TIMER0_COUNT
Table 153. TIMERS_TIMER1_CONTROL_REG (address offset 0x000C)
Bit
Symbol
31:2
RESERVED
1
ENABLE_TIMER0_TRIGGER
UM10858
User manual
COMPANY PUBLIC
Address
Width
Access
offset
(bits)
3FD4h
32
W
3FD8h
32
W
3FDCh
32
W
3FE0h
32
R
3FE4h
32
R
3FE8h
32
W
3FECh
32
W
3FF0h -
32
R
3FFCh
Reset Value
Access Type
0
R
0
R/W
Reset Value
Access Type
0
R
0
R/W
Reset Value
Access Type
0
R
0
R
Reset Value
Access Type
0
R
0
R/W
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Reset value
Description
00000000h
Watchdog set interrupt
00000000h
Timer clear interrupt enable
00000000h
Timer set interrupt enable
00000000h
Timer interrupt status
00000000h
Timer interrupt enable
00000000h
Timer clear interrupt
00000000h
Timer set interrupt
00000000h
Reserved
Description
Reserved
0 – single shot
1 – free running
Description
Reserved
Initial count value of Timer0 in step size of
[2]
0.30 ms
. If set to 0, this feature is disabled.
Description
Reserved
Current count value of Timer0 in step size of
0.30ms
Description
Reserved
1- Timer1 will decrement once when Timer0
reaches its terminal count (assuming that
field TIMER1_TIMEOUT is non-zero in
register TIMERS_TIMER1_TIMEOUT)
0: Timer1 counts independently
© NXP B.V. 2018. All rights reserved.
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