NXP Semiconductors PN7462 series User Manual page 85

NXP Semiconductors
Bit Symbol
5
PVDD_IRQ_VAL
4
PVDD_IRQ_EN
HOSTIF_SW_REGCONTR
3
OL_EN
2:0
HIF_SELECTION
Table 76. PCR_PMU_REG (address offset 0x10)
Bit Symbol
PBF_CONST_LOAD_VA
31:29
L
28
PBF_EN_CONST_LOAD
27
VBATMON_OVERRIDE_VA
L
26
VBATMON_OVERRIDE_EN rw
25 PD_PBF_FIELDSENS
24 BG_TRIM_A
23 BG_TRIM_B
22 BG_TRIM_C
21 BG_TRIM_D
17:20 RESERVED
16 MLDO_LOWPOWER_BG_
EN
15 MLDO_LOWPOWER_VAL
14 MLDO_LOWPOWER_EN
UM10858
User manual
COMPANY PUBLIC
Access Value Description
1: Enable PVDD_M IRQ
0: Disable PVDD_M IRQ
Selects the PVDD voltage trigger level
0: PVDD voltage trigger level 1.8 V
rw 0x00 1: PVDD voltage trigger level 3.3 V
Enables the PVDD IRQ
1: Enable PVDD IRQ
rw 0x00 0: Disable PVDD IRQ
rw 0x00 1: Enabled control of USB D+,D- from ATX_A/B registers
host interface selection
000: No Host interface selected
001: I2C selected as host interface
010: SPI selected as host interface
011: HSU selected as host interface
100 -USB selected as host interface
others - Invalid
rw 0x00
Access Value Description
rw 0x00 configuration bits for constant load on vdhf
Power down signal to connect/disconnect a constant
rw 0x00 load to vdhf
VBUS monitor override value
0: for 2.7 V
rw 0x00 1: for 2.3 V
VBUS monitor override enable
1: Enable for VBUS monitor
0x00 0: Disable VBUS monitor
rw 0x01 1- Enable for pbf_pd_fieldsens
rw 0x00 bandgap trim bit
rw 0x00 bandgap trim bit
rw 0x00 bandgap trim bit
rw 0x00 bandgap trim bit
rw 0x00 Reserved
rw 0x01 Controls mldo bandgap low power signals.
rw 0x00 Value of mldo_low power signal
rw 0x00 Controls mldo low power signals
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Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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