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NXP Semiconductors
Table 215. CLIF_TIMER0_OUTPUT_REG register (address 0090h)
* = reset value
Bit
Symbol
31:25
RESERVED
24
T0_RUNNING
23:20
RESERVED
19:0
T0_VALUE
Table 216. CLIF_TIMER1_OUTPUT_REG register (address 0094h)
* = reset value
Bit
Symbol
31:25
RESERVED
24
T1_RUNNING
23:20
RESERVED
19:0
T1_VALUE
Table 217. CLIF_TIMER2_OUTPUT_REG register (address 0098h)
* = reset value
Bit
Symbol
31:25
RESERVED
24
T2_RUNNING
23:20
RESERVED
19:0
T2_VALUE
Table 218. CLIF_TIMER3_CONFIG_REG register (address 009Ch)
* = reset value
Bit
Symbol
31
T3_RUNNING
30:28
RESERVED
27:8
T3_START_VALUE
7:3
RESERVED
2
T3_START_NOW
1
T3_CLOCK_SEL
0
T3_ENABLE
UM10858
User manual
COMPANY PUBLIC
Access
Value
R
0
R
0*, 1
R
0
R
00000h -
FFFFFh
00h*
Access
Value
R
0
R
0*, 1
R
0
R
00000h -
FFFFFh
00h*
Access
Value
R
0
R
0*, 1
R
0
R
00000h -
FFFFFh
00h*
Access
Value
R
0*, 1
R
0*, 1
R/W
Oh*- FFFFFh
R
0
D
0*, 1
R/W
0*, 1
0
1
R/W
0*, 1
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
Reserved
Indicates that timer T0 is running (busy)
Reserved
Value of 20-bit counter in timer T0
reset value
Description
Reserved
Indicates that timer T1 is running (busy)
Reserved
Value of 20-bit counter in timer T1
reset value
Description
Reserved
Indicates that timer T2 is running (busy)
Reserved
Value of 20-bit counter in timer T2
reset value
Description
Indicates that timer T3 is running (busy)
Reserved
Start value of timer T3
Reserved
Start value of timer T3
Select the timer clock frequency
HFO clock
LFO clock
Enables timer T3
UM10858
© NXP B.V. 2018. All rights reserved.
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