NXP Semiconductors PN7462 series User Manual page 199

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NXP Semiconductors
DPC_GUARD_F
AST_MODE
DPC_GUARD_S
OF_DETECTED
DPC_GUARD_FI
ELD_ON
PCD_SHAPING_
LUT_SIZE
PCD_SHAPING_
LUT
UM10858
User manual
COMPANY PUBLIC
0x20132E
wGuardTimeFastMode
0x201330
wGuardTimeSofDetec
ted
0x201332
wGuardTimeFieldOn
0x2013A8
bSizeOfLUT
0x201368-
dwConfiguration
0x2013a7
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
8:11 are not taken
into account.
R/W
2
Guard time after
AGC fast mode has
been triggered.
This happens in
the following
scenarios:
- End of Receive
- End of Transmit
- After a gear
switch
Time base is 1/20
MHz (Example:
Value of 2000 is
equal to 100us)
Guard time after
R/W
2
SoF or SC
detection. This is to
avoid any DPC
regulation between
SoF/SC and actual
begin of reception.
Time base is
1/20MHz
(Example: Value of
2000 is equal to
100us)
R/W
2
Guard time after
Gear Switch during
FieldOn instruction.
Time base is
1/20MHz
(Example: Value of
2000 is equal to
100us)
Number of
R/W
1
elements for the
PCD Shaping
R/W
64
PCD Shaping
configuration
lookup table: Each
word contains the
following
information:
0..3: DPC Gear
4..7:
TAU_MOD_FALLI
NG (Sign bit + 3-bit
value)
© NXP B.V. 2018. All rights reserved.
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