NXP Semiconductors PN7462 series User Manual page 243

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NXP Semiconductors
14.1.9.8 STATUS_REG
This register indicates the current status of the I2C master.
Table 283. STATUS_REG (address offset 0x001C)
Legend: * reset value; <= mandatory value
Bit
Symbol
31:12
RESERVED
11:8
FIFO_LEVEL
7:6
RESERVED
5
FIFO_EMPTY_STATUS
4
FIFO_FULL_STATUS
3
SCL
2
SDA
1
I2C_MASTER_MODE
0
I2C_BUS_ACTIVE
I2C_BUS_ACTIVE
The I2C_BUS_ACTIVE bit field is set when I2C transmission or reception is enabled
(I2C_ENABLE bit field in the CONTROL_REG register). The I2C_BUS_ACTIVE bit field
is cleared when 2C stop condition is detected.
I2C_MASTER_MODE
The I2C_MASTER_MODE bit field is set when I2C master is configured for I2C
reception. The I2C_MASTER_MODE bit field is cleared when I2C master is configured
for I2C transmission.
SDA
The SDA bit field indicates the current status of sda_a line after 2 flops synchronization.
SCL
The SCL bit field indicates the current status of scl_a line after 2 flops synchronization.
14.1.9.9 CONTROL_REG
This register is used to enable the I2C transmission or reception.
Table 284. CONTROL_REG (address offset 0x0020)
Legend: * reset value; <= mandatory value
Bit
Symbol
31:10
RESERVED
9:0
BYTE_COUNT_CONFIG
UM10858
User manual
COMPANY PUBLIC
Access
Value
Description
R
0x0000000*
reserved
R
0x0*
Indicates the current FIFO level irrespective of I
Mode of operation
R
0x0000000*
Reserved
R
0x1*
Indicates the FIFO empty condition irrespective of I
Mode of operation
R
0x0*
Indicates the FIFO full condition irrespective of I
Mode of operation
R
U*
Current Status of scl_a line
R
U*
Current Status of sda_a line
R
0x0*
I
CONFIG_REG register
R
0x0*
Indicates I
Access
Value
Description
R
0x0000000*
reserved
R
0x000*
This register bit field is used to provide the status of number
of byte currently Transmitted or Received. A maximum of
1023 byte can be transmitted or received in a frame.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
2
C Mode of operation. Status from the IP_MODE bit field of
2
C Transmission or Reception is On-going
UM10858
2
C Master
2
C Master
2
C Master
© NXP B.V. 2018. All rights reserved.
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