NXP Semiconductors PN7462 series User Manual page 91

NXP Semiconductors
Bit Symbol
16 CLOCK_TIMER_ENABLE
15 CLOCK_CRC_ENABLE
14 CLOCK_CLKGEN_ENABLE rw
13 RESERVED
12 CLOCK_RNG_ENABLE
11 CLOCK_CLIF_ENABLE
10 LFO_EN
9:4 LFO_TRIMM
3 EN_SWIO_CLK
2 SELECT_SCR_CTSEQ
1:0 RESERVED
UM10858
User manual
COMPANY PUBLIC
Access Value Description
rw 1: Enable clock source for TIMER
0x01 0: Disable clock source for TIMER
rw 1: Enable clock source for CRC
0x01 0: Disable clock source for CRC
1: Enable clock source for CLKGEN
0x01 0: Disable clock source for CLKGEN
rw 0x01 Set to "0"
rw 1: Enable clock source for RNG
0x01 0: Disable clock source for RNG
rw 1: Enable clock source for CLIF
0x01 0: Disable clock source for CLIF
rw 1: Enable LFO
0x01 0 -Disable LFO
rw 0x20 Trim value for LFO
rw
1: Enables the SWIO clock
0x01
rw
Selects the clock source for the system clock generation
0 - clkXTAL (27.12 MHz)
1 - clkPLL/2 (24 MHz)
0x00
rw
Reserved
0x00
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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