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NXP Semiconductors
Name
PCR_PADSWDIO_REG
INTERNAL_USE
RESERVED
RESERVED
PCR_PADIICM_REG
PCR_ANA_TX_STANDBY_R
EG
PCR_ANA_TXPROT_REG
INTERNAL_USE
PCR_SPIM_REG
PCR_CTIF_REG
PCR_HOSTIF_SAVE1_REG
PCR_HOSTIF_SAVE2_REG
PCR_TXLDO_MON_REG
PCR_BOOT2_REG
PCR_GPREG3_REG
PCR_GPREG4_REG
PCR_GPREG5_REG
PCR_GPREG6_REG
PCR_GPREG7_REG
PCR_GPIO_INT_ACTIVE_L
OW_REG
PCR_GPIO_INT_LEVEL_SE
NSE_REG
PCR_GPIO_INT_ACTIVE_B
OH_EDGE_REG
PCR_SELECT_SYSTEMCLO
CK
PCR_ADV_RFLD_REG
PCR_ADV_RFLD_TEST_RE
G
PCR_INT_CLR_ENABLE_RE
G
PCR_INT_SET_ENABLE_RE
G
PCR_INT_STATUS_REG
UM10858
User manual
COMPANY PUBLIC
Address
Width
Access
(bits)
Offset
0x0094
32
rw-
0x0098
32
rw-
0x009C
32
rw-
0x00A0
32
rw-
0x00A4
32
rw-
0x00A8
32
rw-
0x00AC
32
rw-
0x00B0
32
rw-
0x00B4
32
rw-
0x00B8
32
rw-
0x00BC
32
rw-
0x00C0
32
rw-
0x00C4
32
rw-
0x00C8
32
rw-
0x00CC
32
rw-
0x00D0
32
rw-
0x00D4
32
rw-
0x00D8
32
rw-
0x00DC
32
rw-
0x00E0
32
rw-
0x00E4
32
rw-
0x00E8
32
rw-
0x00EC
32
rw-
0x00F0
32
rw-
0x00F4
32
rw-
0x3FD8
32
-wm
0x3FDC
32
-wm
0x3FE0
32
r-m
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset value
Description
0x00000006
SWDIO pad slew rate configuration
0x00000006
For internal use
0x0000020C
Reserved
0x00000008
Reserved
0x00000280
I2C master pad configuration
0x00000000
CLIF standby GSN value selection
CLIF configuration related to power
0x00000001
down
0x00000041
For internal use
0x00000040
SPIM master pad configuration
0x00000000
CTIF presense detection pull-up
host interface Tx/RX divider value
0x00000000
storage during standby
host interface clock value storage during
0x00000000
standby
0x00000008
TXLDO sequence management
0x00000000
BOOT reason register extention.
0x00000000
general-purpose register 3 for SW
0x00000000
general-purpose register 4 for SW
0x00000000
general-purpose register 5 for SW
0x00000000
general-purpose register 6 for SW
0x00000000
general-purpose register 7 for SW
register to program is GPIO interrupts
are active low level/ falling edge
0x00000000
sensitive
register to program if GPIO interrupts are
0x00000000
level sensitive.
register to program if GPIO interrupts are
0x00000000
both edge sensitive
register to program the source for
0x00000001
system clock.
register for configuring advanced RFLD
0x00000000
detection FSM
configuration bits for testing advanced
0x00000000
RFLD detection FSM
0x00000000
interrupt clear enable
0x00000000
interrupt set enable
0x00000000
interrupt status
UM10858
© NXP B.V. 2018. All rights reserved.
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