NXP Semiconductors PN7462 series User Manual page 23

NXP Semiconductors
Bit Symbol
27:16 ee_CRC_DAT_ADDR_END
15:12 RESERVED
11:0 ee_CRC_DAT_ADDR_START
Table 13. EE_CRC_1_COD_INIT (address offset 0x0018h)
Bit Symbol
31:0 ee_crc_1_COD_INIT
Table 14. EE_CRC_1_COD (address offset 0x001Ch)
Bit Symbol
31:0 ee_crc_1_COD
Table 15. EE_CRC_1_COD_ADDR (address offset 0x0020h)
Bit Symbol
31:16 ee_CRC_1_COD_ADDR_END
15:0 ee_CRC_1_COD_ADDR_START
Table 16. EE_CRC_0_COD_INIT (address offset 0x0024h)
Bit Symbol
31:0 ee_crc_0_COD_INIT
Table 17. EE_CRC_0_COD (address offset 0x0028h)
Bit Symbol
31:0 ee_crc_0_COD
UM10858
User manual
COMPANY PUBLIC
Access Value
R/W 7FFh
- 0
R/W 000h
Access Value
R/W FFFFh
Access Value
R FFFFh
Access Value
R/W 4FFFh
R/W 0000h
Access Value
R/W FFFFh
Access Value
R FFFFh
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Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
EEPROM CRC calculation end address
corresponding to a native 16-bit data
access (AHB memory map divided by 2)
Reserved
EEPROM CRC calculation start address
corresponding to a native 16-bit data
access (AHB memory map divided by 2)
Description
FLASH_1 CRC Init Value loaded as soon
as CRC_CLEAR_1_COD is high,
meaning that FLASH_1 CRC must be set
before CRC_CLEAR_1_COD.
Description
FLASH_1 CRC value
Description
FLASH_1 CRC calculation end address
corresponding to a native 32-bit data
access (AHB Memory Map divided by 8)
FLASH_1 CRC calculation start address
corresponding to a native 32-bit data
access (AHB memory map divided by 8)
Description
FLASH_0 CRC Init value loaded as soon
as CRC_CLEAR_0_COD is high,
meaning that FLASH_0 CRC must be set
before CRC_CLEAR_0_COD.
Description
FLASH_0 CRC value
UM10858
© NXP B.V. 2018. All rights reserved.
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