Table of Contents
Advertisement
NXP Semiconductors
• Crystal Oscillator or External clock
• USB Clock Disable
7.2.3 USB PLL frequency calculation
The USB PLL soft decoder selects pre-defined divider ratios and corresponding
bandwidth of the PLL to guarantee stability. The soft decoder can only select two sets of
divider parameters in order to have a ~48 MHz output clock from a 27.12 MHz input clock
(Clkout=Clkinx(M/(NxP))).
CLKGEN_USB_PLL_CONTROL_REG.usb_pll_mnp_sel = '0' : M=69, N=13,P=3
Clkout=Clkinx(M/N.P) = 27.12 MHz × (69/(13 × 3)) = 48 MHz
CLKGEN_USB_PLL_CONTROL_REG.usb_pll_mnp_sel = '1' : M=92, N=13,P=4.
Clkout=Clkinx(M/N.P) = 27.12 MHz × (92/(13 × 4)) ~ 47.9815 MHz
The Soft Decoder can be bypassed in order to have the full control of the divider ratios.
When CLKGEN_USB_PLL_CONTROL_REG.usb_pll_mnp_dec_selection is set to '1'
M,N,P divider ratios are coming from CLKGEN_USB_PLL_MDEC_WO_SOFTDEC and
CLKGEN_USB_PLL_NDEC_PDEC_WO_SOFTDEC registers.
7.2.4 USB PLL Activation Sequence
The Activation Sequence with default MNP parameters comprises following steps:
1. Put the PLL in Power Down Mode
2. Enable the PLL input buffer
3. Set the expected PLL input clock frequency for the clock detector by setting the
UM10858
User manual
COMPANY PUBLIC
CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_CLKOUT_SELECT = '00'
CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_CLKOUT_SELECT = '01'
CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_CLKOUT_SELECT = '10'
or '11'
CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_PD = '1'
CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_INPUT_BUFFER_ENABLE = '1'
detection window length and the amount of expected detected input clock rising
edges in this detection window respectively defined by the following registers
CLKGEN_INPUT_CLOCK_DETECTOR_CONTROL_REG.
By default, these registers are set to detect a 27.12 MHz input clock.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
59 of 345
Advertisement
Table of Contents
