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NXP Semiconductors
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HOSTIF_DBG_RX_REG
This register is used for the debug received data.
Table 346. HOSTIF_DBG_RX_REG (address offset 0x0074)
Bit
31:5
HOSTIF_DBG_RX_REG
This register is used to indicate the debug receive address.
Table 347. HOSTIF_DBG_RX_ADDR_REG (address offset 0x0078)
Bit
31:16
15:14
13:0
HOSTIF_INT_CLR_ENABLE_REG
This register is a collection of clear interrupt enable commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 348. HOSTIF_INT_CLR_ENABLE_REG (address offset 0x3FD8)
Bit
31:27
26
25
24
23
UM10858
User manual
COMPANY PUBLIC
Can be overwritten by FW using either register HOSTIF_SET_DATA_READY_REG or register
HOSTIF_CLR_DATA_READY_REG.
The buffer manager can only clear this bit.
The buffer manager can only set this bit.
Symbol
RX_REG
Symbol
RESERVED
WR_PTR
WR_ADDR
Symbol
RESERVED
HSU_RX_FER_CLR_
ENABLE
BUFFER_CFG_CHAN
GED_ERROR_CLR_E
NABLE
AHB_WR_SLOW_CLR
_ENABLE
AHB_RD_SLOW_CLR
_ENABLE
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Access
Reset
Description
Value
R
0
Contains byte the last received bytes to be
written into memory as one word
Access
Reset
Description
Value
R
0
Reserved
R
0
Pointer to next byte to write into RX_REG
(next byte inside word to write to memory)
R
0
Next AHB write address
Access
Reset
Description
Value
W
0
Reserved
W
0
1 - clear enable for HSU RX frame error
interrupt0 - no effect
W
0
1 - clear enable for buffer config changed
during use interrupt
0 - no effect
W
0
1 - clear enable for slow AHB during write
operation interrupt
0 - no effect
W
0
1 - clear enable for slow AHB during read
operation interrupt
0 - no effect
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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