NXP Semiconductors PN7462 series User Manual page 104

NXP Semiconductors
Bit Symbol
0
CT_ENABLE_PUP
Table 115. PCR_HOSTIF_SAVE1_REG (address offset 0xBC)
Bit Symbol
31:11 RESERVED
10 HSU_TX_DIVIDER
9:0 HSU_RX_DIVIDER
Table 116. PCR_HOSTIF_SAVE2_REG (address offset 0xC0)
Bit Symbol
31:24 RESERVED
23:11 HSU_TX_CLK_CORRECT
10:0 HSU_RX_CLK_CORRECT
Table 117. PCR_TXLDO_MON_REG (address offset 0xC4)
Bit Symbol
31:4 RESERVED
3 WELL_MNGT
2
SRC_5V_MONITOR
1
THRES_5V_MONITOR
0
EN_5V_MONITOR
Table 118. PCR_BOOT2_REG (address offset 0xC8)
Bit Symbol
31:24 SPARE_CELL3
23 BOOT_REASON_ACTIVE_
HPD
22 BOOT_REASON_VBUS_L
OW
21:0 SPARE_CELL2
UM10858
User manual
COMPANY PUBLIC
Access Value Description
Value of ct_pres_enable_pup_i coming from CTIF is
latched and is used to detect card activity during standby
and suspend modes if CTIF is enabled as wakeup
source
r- 0x00 1: CT pres pull up enabled
Access Value Description
rw 0x00 Reserved
rw 0x00 TX divider save (only save reg for stby)
rw 0x00 RX Divider save (only save reg for stby)
Access Value Description
rw 0x00 Reserved
rw 0x00 clock correction for TX (only save reg for stby)
rw 0x00 Clock correction for RX (only save reg for stby)
Access Value Description
rw 0x00 Reserved
rw 0x01 TXLDO well mngt
Input of the 5 V monitor.
1: TVDD is the source of 5 V monitor
rw 0x00 0: VUP_TX is the source of 5 V monitor
Comparator threshold selector
rw 0x00 1: Threshold of 5 V Monitor is 5 V
1: Enable the 5 V monitor on TVDD
rw 0x00 0: Disable the 5 V monitor on TVDD
Access Value Description
rw 0x00 Third set of spare cells.
r- 0x00 1: Boot because of coming out of ACTIVE_HPD
1: Boot because of VBUS going low in suspend or
r- 0x00 standby.
rw 0x00000 Second set of space cells
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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