NXP Semiconductors PN7462 series User Manual page 217

NXP Semiconductors
13.6.2.4 Register ct_fcr_reg (FIFO Control Register)
This configuration register defines the FIFO threshold (interrupt signaled by the ft bit of
register ct_usr1_reg) and the number of repetition of character in case of Parity Error
(interrupt signaled by the pe bit of register ct_usr1_reg).
Table 252. ct_fcr_reg (address 000Ch) bit description
Bit Symbol Access
31:8 RESERVED -
7:5 PEC2 - PEC0 R/W
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Fig 41. ETU (and card clock CLK) generation
Reset Description
Value
0 Reserved
000b Parity Error Count:
- In protocol T = 0:
Set the number of allowed repetitions in reception or transmission mode before
setting pe in ct_usr1_reg. The value 000 indicates that, if only one parity error
has occurred, bit pe is set at logic 1; the value 111 indicates that bit pe will be
set at logic 1 after 8 parity errors.
•
If a correct character is received before the programmed error number is
reached, the error counter will be reset.
•
If the programmed number of allowed parity errors is reached, bit pe in
register ct_usr1_reg will be set at logic 1.
•
If a transmitted character has been nacked by the card, then the Contact
UART will automatically retransmit it up to a number of times equal to the value
programmed in bits PEC(2:0); the character will be resent at 15 ETU.
•
If a transmitted character is considered as correct by the card after having
been naked a number of times less than the value programmed in bits
PEC(2:0) +1, the error counter will be reset.
•
If a transmitted has been naked by the card a number of times equal to the
value programmed in bits PEC(2:0) +1, the transmission stops and bit pe in
register ct_usr1_reg is set at logic 1. The firmware is supposed to deactivate
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
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