NXP Semiconductors PN7462 series User Manual page 305

NXP Semiconductors
Bit
22
21
20:17
16
15
14:11
10:7
6
UM10858
User manual
COMPANY PUBLIC
Symbol Access
AHB_ERROR_CLR_E W
NABLE
WATERLEVEL_REAC W
HED_CLR_ENABLE
RX_BUFFER_OVERF W
LOW_CLR_ENABLE
CRC_NOK_CLR_ENA W
BLE
TX_TIMEOUT_CLR_E W
NABLE
RX_FRAME_OVERFL W
OW_CLR_ENABLE
RX_FRAME_UNDERF W
LOW_CLR_ENABLE
TX_FRAME_NOT_AV W
AILABLE_CLR_ENAB
LE
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Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset Description
Value
0 1 - clear enable for ahb_error (hresp=1,
oraddress overflow) interrupt
0 - no effect
0 1 - clear enable for water level reached
interrupt
0 - no effect
0 0001 - clear enable for max buffer size
interrupt for RX buffer 0
0010 - clear enable for max buffer size
interrupt for RX buffer 1
0100 - clear enable for max buffer size
interrupt for RX buffer 2
1000 - clear enable for max buffer size
interrupt for RX buffer 3
0000 - no effect
0 1 - clear enable for data-link Layer CRC
error interrupt
0 - no effect
0 1 - clear enable for inter-character timeout
(TIC) exceeded on transmitted frame
interrupt
0 - no effect
0 0001 - clear enable for frame overflow
interrupt for RX buffer 0
0010 - clear enable for frame overflow
interrupt for RX buffer 1
0100 - clear enable for frame overflow
interrupt for RX buffer 2
1000 - clear enable for frame overflow
interrupt for RX buffer 3
0000 - no effect
0 0001 - clear enable for frame underflow
interrupt for RX buffer 0
0010 - clear enable for frame underflow
interrupt for RX buffer 1
0100 - clear enable for frame underflow
interrupt for RX buffer 2
1000 - clear enable for frame underflow
interrupt for RX buffer 3
0000 - no effect
0 1 - clear enable for TX frame not available
interrupt
0 - no effect
UM10858
© NXP B.V. 2018. All rights reserved.
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