NXP Semiconductors PN7462 series User Manual page 308

NXP Semiconductors
Bit
3:0
HOSTIF_INT_STATUS_REG
This register is a collection of interrupt status commands. Writing 1 to this register does
set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has no
effect.
Table 350. HOSTIF_INT_STATUS_REG (address offset 0x3FE0)
Bit
31:27
26
25
24
23
22
21
20:17
16
UM10858
User manual
COMPANY PUBLIC
Symbol Access
EOR_SET_ENABLE W
Symbol Access
RESERVED W
HSU_RX_FER_STATU W
S
BUFFER_CFG_CHAN
W
GED_ERROR_STATU
S
AHB_WR_SLOW_STA W
TUS
AHB_RD_SLOW_STA W
TUS
AHB_ERROR_STATU W
S
WATERLEVEL_REAC W
HED_STATUS
RX_BUFFER_OVERF W
LOW_STATUS
CRC_NOK_STATUS W
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Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset Description
Value
0 1 - set enable for End of Reception in
buffer N (0<=N<=3) interrupt
0001 - set enable for EOR interrupt for RX
buffer 0
0010 - set enable for EOR interrupt for RX
buffer 1
0100 - set enable for EOR interrupt for RX
buffer 2
1000 - set enable for EOR interrupt for RX
buffer 3
0000 - no effect
Reset Description
Value
0 Reserved
0 HSU RX frame error interrupt
Buffer configuration changed during use
0
interrupt
0 Slow AHB during write operation interrupt
0 Slow AHB during read operation interrupt
0 Ahb_error (hresp=1, or address overflow)
interrupt
0 Water level reached interrupt status
0 0001 - maximum buffer size exceeded
interrupt status for RX buffer 0
0010 - maximum buffer size exceeded
interrupt status for RX buffer 1
0100 - maximum buffer size exceeded
interrupt status for RX buffer 2
1000 - maximum buffer size exceeded
interrupt status for RX buffer 3
0 Data-link layer CRC error interrupt status
UM10858
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