NXP Semiconductors PN7462 series User Manual page 324

NXP Semiconductors
15.4.2 Register description
The following chapter describes the register on a bit level.
15.4.2.1 USB device command/ Status register
Table 356. USB device command/ Status register (address offset = 0x00)
Reset value: 0x00000800
Bit Symbol
6:0 DEV_ADDR
7 DEV_EN
8 SETUP
9 PLL_ON
10 RESERVED
11 LPM_SUP
12 IntOnNAK_AO
13 IntOnNAK_AI
14 IntOnNAK_CO
15 IntOnNAK_CI
UM10858
User manual
COMPANY PUBLIC
Value Description
USB device address. After bus reset, the address is reset to 0x00. If
the enable bit is set, the device will respond on packets for function
address DEV_ADDR. When receiving a SetAddress Control
Request from the USB host, firmware must program the new
address before completing the status phase of the SetAddress
control request.
USB device enable. If this bit is set, the hardware will start
responding on packets for function address DEV_ADDR
SETUP token received. If a SETUP token is received and
acknowledged by the device, this bit is set. As long as this bit is set
all received IN and OUT tokens will be NAKed by hardware. SW
must clear this bit by writing a one. If this bit is zero, hardware will
handle the tokens to the CTRL EP0 as indicated by the CTRL EP0
IN and OUT data information programmed by SW.
Always PLL Clock on:
0 USB_NeedClk functional
USB_NeedClk always „1‟. Clock will not be stopped in case of
1
suspend
Reserved
LPM supported:
0 LPM not supported. hardware returns no handshake when receiving
an LPM token
1 LPM supported
Interrupt on NAK for interrupt and bulk OUT EP
0 Only acknowledged packets generate an interrupt
1 Both acknowledged and NAKed packets generate interrupts
Interrupt on NAK for interrupt and bulk IN EP
0 Only acknowledged packets generate an interrupt
1 Both acknowledged and NAKed packets generate interrupts
Interrupt on NAK for control OUT EP
0 Only acknowledged packets generate an interrupt
1 Both acknowledged and NAKed packets generate interrupts
Interrupt on NAK for control IN EP
0 Only acknowledged packets generate an interrupt
1 Both acknowledged and NAKed packets generate interrupts
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Reset
Value
0
0
0
0
0
1
0
0
0
0
© NXP B.V. 2018. All rights reserved.
Access
R/W
R/W
R/W/C
R/W
RO
R/W
R/W
R/W
R/W
R/W
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