NXP Semiconductors PN7462 series User Manual page 242

NXP Semiconductors
TXMODE_THRESHOLD
FIFO Threshold level for interrupt request generation when I2C master is configured for
transmission mode.
1. TXMODE_THRESHOLD register field is valid only during I2C transmission.
2. Interrupt request is generated when the TXMODE_THRESHOLD equals the I2C
3. Byte granularity will be interpreted by the BYTECOUNT_CONFIG_REG.
RXMODE_THRESHOLD
FIFO threshold level for interrupt request generation when I2C master is configured for
reception mode.
1. RXMODE_THRESHOLD register field is valid only during I2C transmission.
2. Interrupt request is generated when the RXMODE_THRESHOLD equals the I2C
3. Byte granularity must be interpreted by the BYTECOUNT_CONFIG_REG.
14.1.9.6 BYTECOUNT_CONFIG_REG
This register's function is to configure the number of bytes to be transmitted or received.
Table 281. BYTECOUNT_CONFIG_REG (address offset 0x0014)
Legend: * reset value; <= mandatory value
Bit Symbol
31:10 RESERVED
9:0 BYTE_COUNT_CONFIG
14.1.9.7 BYTECOUNT_STATUS_REG
This register reflects the status of number of bytes being transmitted or received.
Table 282. BYTECOUNT_STATUS_REG (address offset 0x0018)
Legend: * reset value; <= mandatory value
Bit Symbol
31:10 RESERVED
9:0 BYTE_COUNT_CONFIG
UM10858
User manual
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master internal FIFO.
master internal FIFO.
Access Value
R 0x0000000*
R/W 0x000*
Access Value
R 0x0000000*
R 0x000*
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Rev. 1.4 — 14 May 2018
Description
reserved
This register bit field is used to configure the number of byte
to be Transmitted or Received. A maximum of 1023 byte can
be transmitted or received in a frame.
Description
reserved
This register bit field is used to provide the status of number
of byte currently Transmitted or Received. A maximum of
1023 byte can be transmitted or received in a frame.
314514
UM10858
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