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NXP Semiconductors
Bit
Symbol
22
RX_SC_DET_IRQ_CLR_ENA
BLE
21
RX_SOF_DET_IRQ_CLR_EN
ABLE
20
RX_EMD_IRQ_CLR_ENABLE W
19
TIMER3_IRQ_CLR_ENABLE
18
TIMER2_IRQ_CLR_ENABLE
17
TIMER1_IRQ_CLR_ENABLE
16
TIMER0_IRQ_CLR_ENABLE
15
CLOCK_ERROR_IRQ_CLR_
ENABLE
[1]
14
INTERNAL_USE
[1]
13
INTERNAL_USE
12
RF_ACTIVE_ERROR_IRQ_C
LR_ENABLE
11
TX_RFON_IRQ_CLR_ENABL
E
10
TX_RFOFF_IRQ_CLR_ENAB
LE
9
RFON_DET_IRQ_CLR_ENAB
LE
8
RFOFF_DET_IRQ_CLR_ENA
BLE
7:6
RESERVED
5
STATE_CHANGE_IRQ_CLR_
ENABLE
CARD_ACTIVATED_IRQ_CL
4
R_ ENABLE
3
MODE_DETECTED_IRQ_CL
R_ENABLE
2
IDLE_IRQ_CLR_ENABLE
1
TX_IRQ_CLR_ENABLE
0
RX_IRQ_CLR_ENABLE
[1]
Bit-field are either set by HAL or use default value from CLIF EEPROM default settings
UM10858
User manual
COMPANY PUBLIC
Access
Value
Description
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
Writing 1 to this register does clear the corresponding IRQ
W
0, 1
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE
W
0, 1
For internal use
W
0, 1
For internal use
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0
Reserved
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
Writing 1 to this register does clear the corresponding IRQ
W
0, 1
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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