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NXP Semiconductors
• The watchdog interrupt is connected to the ARM subsystem NMI (non-mask able
• The watchdog eventually sends a reset signal to the PCR to reset the chip if the
• The watchdog reset is enabled by software, requires a system reset or a Watchdog
11.4 Register overview and description
11.4.1 Register overview
Table 149. Timer register overview (base address 0x4001 C000)
Name
TIMERS_TIMER0_CONTROL_REG
TIMERS_TIMER0_TIMEOUT_REG
TIMERS_TIMER0_COUNT_REG
TIMERS_TIMER1_CONTROL_REG
TIMERS_TIMER1_TIMEOUT_REG
TIMERS_TIMER1_COUNT_REG
TIMERS_TIMER2_CONTROL_REG
TIMERS_TIMER2_TIMEOUT_REG
TIMERS_TIMER2_COUNT_REG
TIMERS_TIMER3_CONTROL_REG
TIMERS_TIMER3_TIMEOUT_REG
TIMERS_TIMER3_COUNT_REG
TIMERS_WDOG_CONTROL_REG
TIMERS_WDOG_TIMEOUT_REG
TIMERS_WDOG_TRIGGER_INT_REG
TIMERS_WDOG_COUNT_REG
RESERVED
RESERVED
RESERVED
TIMERS_WDOG_INT_STATUS_REG
TIMERS_WDOG_INT_CLR_STATUS_REG
UM10858
User manual
COMPANY PUBLIC
Interrupt).
threshold setting is not periodically reloaded by the FW.
reset/interrupt to be disabled. When enabled, The CPU must pulse the kick bit to
reload the watchdog counter before it expires.
Address
offset
0000h
0004h
0008h
000Ch
0010h
0014h
0018h
001Ch
0020h
0024h
0028h
002Ch
0030h
0034h
0038h
003Ch
0040h
0044h
0048h -
3FC8h
3FCCh
3FD0h
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Width
Access
Reset value
(bits)
32
R/W
0000000h
32
R/W
0000000h
32
R
0000000h
32
R/W
0000000h
32
R/W
0000000h
32
R
0000000h
32
R/W
0000000h
32
R/W
0000000h
32
R
0000000h
32
R/W
0000000h
32
R/W
0000000h
32
R
0000000h
32
R/W
0000000h
32
R/W
0000000h
32
R/W
0000000h
32
R
0000000h
32
R/W
00000000h
32
R
00000000h
32
R
00000000h
32
R
00000000h
32
W
00000000h
314514
UM10858
PN7462 family HW user manual
Description
Control of Timer 0
Timeout value of Timer0
Current count value of
Timer0
Control of Timer1
Timeout value of Timer1
Current count value of
Timer1
Control of Timer 2
Timeout value of Timer2
Current count value of
Timer2
Control of Timer3
Timeout value of Timer3
Current count value of
Timer3
Control of Watchdog Timer
Timeout value of Watchdog
Timer
Count value of Watchdog
Timer which triggers
interrupt
Current count value of
Watchdog Timer
Reserved
Reserved
Reserved
Watchdog interrupt status
Watchdog clear interrupt
© NXP B.V. 2018. All rights reserved.
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