NXP Semiconductors PN7462 series User Manual page 229

NXP Semiconductors
13.6.2.21 Register ct_fsr_reg (FIFO Status register)
This status register enables to know how many bytes are present into the FIFO; it doesn't
generate any interrupt.
Table 270. ct_fsr_reg (address 005Ch) bit description
Bit Symbol Access
31:6 RESERVED -
5:0 ffl5 – ffl0 R
13.6.2.22 Register ct_msr_reg (Mixed Status Register)
This status register is intended for polling; it doesn't generate any interrupt.
Table 271. ct_msr_reg (address 0060h) bit description
Bit Symbol Access
31:3 RESERVED -
2 INTAUX R
1 BGT R
0 PRES R
13.6.2.23 Register ct_usr1_reg (UART Status Register 1)
This register is an interrupt register (together with ct_usr2_reg register): these bits
coming from the Contact UART core are used to manage the reception & transmission of
characters. Read this register enables to know what the cause of the interrupt is. The bits
are set to logic 1 by hardware and set to logic 0 by reading (with a hardware mechanism
avoiding the loss of incoming interrupt while reading).
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Reset Description
Value
0 reserved
0 0000b FIFO Fulfilment Level
Gives the number of bytes present into the FIFO.
Reset Description
Value
0 reserved
0b Auxiliary interrupt
Bit INTAUX is the copy of pin INTAUX.
0b Block Guard Time
In protocol T = 1, bit BGT is linked with a 22-ETU counter, which is started
at every start bit on pin I/O. Bit BGT is set to logic level one, if the count is
finished before the next start bit. This helps to verify that the card has not
answered before 22 ETU after the last transmitted character, or that the
reader is not transmitting a character before 22 ETU after the last received
character.
In protocol T = 0, bit BGT is linked with a 16-ETU counter, which is started
at every start bit on pin I/O. Bit BGT is set to logic level one, if the count is
finished before the next start bit. This helps to verify that the card has not
answered before 16 ETU after the last transmitted character, or that the
reader is not transmitting a character before 16 ETU after the last received
character.
0b PRESence
Set to logic 1 when the card is present.
Set to logic 0 when the card is not present or has been removed.
Remark: the bits pres_pup_en and pres_con_no in ct_ssr_reg register
should have been set prior to any check of card presence.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
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