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NXP Semiconductors
HOSTIF_WATERLEVEL_REG
This register is to used indicate the water level.
Table 342. HOSTIF_WATERLEVEL_REG (address offset 0x0064)
Bit
31:11
10:0
HOSTIF_SET_DATA_READY_REG
This register is used to set data ready flags for buffers.
Table 343. HOSTIF_SET_DATA_READY_REG (address offset 0x0068)
Bit
31:5
4
3
2
1
0
[1]
[2]
HOSTIF_CLR_DATA_READY_REG
This register is used to clear data ready flags for buffers.
Table 344. HOSTIF_CLR_DATA_READY_REG (address offset 0x006C)
Bit
31:5
4
3
UM10858
User manual
COMPANY PUBLIC
Symbol
RESERVED
WATERLEVEL
Symbol
RESERVED
SET_TX_DATA_READ
[1]
Y
SET_RX3_DATA_REA
[2]
DY
SET_RX2_DATA_REA
[2]
DY
SET_RX1_DATA_REA
[2]
DY
SET_RX0_DATA_REA
[2]
DY
Setting this bit will only cause bit HOSTIF_DATA_READY_STATUS_REG.TX_DATA_READY to be set if
the buffer is not in use by the buffer manager (HOSTIF_STATUS_REG.TX_BUFFER_LOCK = 0).
Setting this bit will only cause bit HOSTIF_DATA_READY_STATUS_REG.RX<n>_DATA_READY to be
set if the buffer is not in use by the buffer manager (HOSTIF_STATUS_REG.RX<n>_BUFFER_LOCK =
0).
Symbol
RESERVED
CLR_TX_DATA_READ
[1]
Y
CLR_RX3_DATA_REA
[2]
DY
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Access
Reset
Description
Value
R
0
Reserved
R/W
0
Number of bytes received in incoming
frame before triggering an interrupt (pre-
empting EOR). If set to 0, this feature is
disabled.
Access
Reset
Description
value
R
0
Reserved
W
0
Set TX_DATA_READY
W
0
Set RX3_DATA_READY
W
0
Set RX2_DATA_READY
W
0
Set RX1_DATA_READY
Set RX0_DATA_READY
W
0
Access
Reset
Description
value
R
0
Reserved
W
0
Clear TX_DATA_READY
W
0
Clear RX3_DATA_READY
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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