Clif Pll - NXP Semiconductors PN7462 series User Manual

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4. Enable Input Clock Detector
5. Poll for CLKGEN_STATUS_REG.CLK_IN_DETECT_DONE = '1' (after ~5.2 us by
6. Check that CLKGEN_STATUS_REG.CLK_IN_OK = '1'.
7. Disable the Input Clock Detector
8. Exit the PLL from the Power Down Mode
9. Enable the PLL
10. Poll for CLKGEN_STATUS_REG.PLL_LOCK = '1' to confirm the lock status of the

7.3 CLIF PLL

The integrated CLIF PLL is designed to generate a low-noise 27.12 MHz clock, which is
used as time reference for the Contactless Interface when PN7462 family is in reader
mode or acting as ISO/IEC 18092 initiator.
The frequency value of the reference clock that is fed, can be selected using
CLKGEN_CLIF_PLL_GLOBAL_CONTROL_REG register between:
1. Crystal oscillator output (default)
2. External clock input
The CLIF PLL output can be configured using
CLKGEN_CLIF_PLL_GLOBAL_CONTROL_REG registers as:
1. Fractional PLL output
2. XTAL oscillator output Clock
3. Regular PLL output
4. PLL input
The clock generator module provides a PLL/XTAL clock presence indicator signal to the
CLIF. This signal is active when the clock coming from the PLL or XTAL, or a
UM10858
User manual
COMPANY PUBLIC
CLKGEN_INPUT_CLOCK_DETECTOR_CONTROL_REG.USB_CLK_DETECT_EN
ABLE = '1'.
default). This will only indicate that the detection procedure is finished, not that there
is clock and/or the frequency is the expected one.
This will indicate if there is a clock of a frequency higher or equals to the expected one
(27.12 MHz by default) at the input of the PLL. If this bit is 0 while
CLK_IN_DETECT_DONE is high, this means either that there is no clock or that the
clock has a frequency lower than the expected one (27.12 MHz), which will hamper
the PLL functionality or give an unwanted PLL output frequency value.
CLKGEN_USB_PLL_CONTROL_REG. USB_CLK_DETECT_ENABLE = '0'.
CLKGEN_USB_PLL_CONTROL_REG.PLL_PD = '0'
CLKGEN_USB_PLL_CONTROL_REG.PLL_CLKEN = '1'
PLL.
Software can start a new PLL input clock detection at any time by generating a low to
high transition on the
CLKGEN_INPUT_CLOCK_DETECTOR_CONTROL_REG.USB_CLK_DETECT_ENA
BLE register.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
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PN7462 family HW user manual
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