NXP Semiconductors PN7462 series User Manual page 24

NXP Semiconductors
Table 18. EE_CRC_0_COD_ADDR (address offset 0x002Ch)
Bit Symbol
31:16 ee_CRC_0_COD_ADDR_END
15:0 ee_CRC_0_COD_ADDR_START R/W
Table 19. EE_CRC_0_COD_ADDR (address offset 0x002Ch)
Bit Symbol
31:16 ee_CRC_0_COD_ADDR_END
15:0 ee_CRC_0_COD_ADDR_START R/W
Table 20. EE_TRIMM (address offset 0x003Ch)
Bit Symbol
31:24 RESERVED
23:20 hvtrimw_1_COD
19:16 hvtrime_1_COD
15:12 hvtrimw_0_COD
11:8 hvtrime_0_COD
7:4 hvtrimw_dat
3:0 hvtrime_dat
Table 21. EE_ECC_PF_AHB_ERROR_ADDR (address offset 0x0044h)
Bit Symbol
31:18 RESERVED
17:0 ECC_PF_AHB_ERROR_ADDR
Table 22. EE_INT_CLR_ENABLE (address offset 0x0FD8h)
Bit Symbol
31:10 RESERVED
9 EE_ECC_READ_NOT_CORRE
CT_1_COD_INT_CLR_ENABLE
8 EE_ECC_READ_INVALID_1_C
OD_INT_CLR_ENABLE
UM10858
User manual
COMPANY PUBLIC
Access Value
R/W 4FFFh
0000h
Access Value
R/W 4FFFh
0000h
Access Value
- 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Access Value
- 0
R 0
Access Value
- 0
W 0
W 0
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Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
FLASH_0 CRC calculation end address
corresponding to a native 32-bit data
access (AHB memory map divided by 8)
FLASH_0 CRC Calculation start address
corresponding to a native 32-bit data
access (AHB memory map divided by 8)
Description
FLASH_0 CRC calculation end address
corresponding to a native 32-bit data
access (AHB memory map divided by 8)
FLASH_0 CRC calculation start address
corresponding to a native 32-bit data
access (AHB memory map divided by 8)
Description
Reserved
HV trimming value program for the
FLASH_1
HV trimming value Erase for the FLASH_1
HV trimming value Program for the
FLASH_0
HV trimming value Erase for the FLASH_0
HV trimming value Program for the
EEPROM
HV trimming value Erase for the EEPROM
Description
Reserved
AHB address for which a flash read data
was detected as invalid or corrected by
the ECC module.
Description
Reserved
FLASH_1 not correct ECC read interrupt
clear enable command
FLASH_1 Invalid ECC Read interrupt
clear enable command
UM10858
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