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NOTES
14.3.4.6 EOR
When the EOF logic is asserted high and the Buffer Manager has written the last word to
the buffer, an EOR event is generated. The EOR_STATUS field in register
HOSTIF_INT_STATUS_REG is set.
14.3.4.7 EOT
When the EOF logic is asserted high and the last word has been sent from the TX buffer,
the Buffer Manager generates an EOT event. The EOT_STATUS field in register
HOSTIF_INT_STATUS_REG is set and bit
HOSTIF_STATUS_REG.TX_BUFFER_LOCK is cleared logic low.
14.3.4.8 Waterlevel reached
If the field WATERLEVEL in register HOSTIF_WATERLEVEL_REG is non-zero, then the
Buffer Manager generates a Waterlevel Reached event when the number of bytes
received is equal to WATERLEVEL. The field WATERLEVEL_REACHED_STATUS in
register HOSTIF_INT_STATUS_REG is set. An EOR event is not generated until the end
of the frame as normal.
14.3.4.9 RX frame underflow
If fewer bytes have been received than indicated in the Frame Length of the Data-link
header when the EOF logic is asserted high, the buffer manager sets
RX_FRAME_UNDERFLOW_STATUS in register HOSTIF_INT_STATUS_REG. The
frame is discarded by not setting
HOSTIF_DATA_READY_STATUS_REG.RX<n>_DATA_READY. An EOR event is not
generated. The EOR_STATUS flag in register HOSTIF_INT_STATUS_REG maintains
logic low.
Note that there is no RX Frame Underflow detection in native mode.
14.3.4.10 RX frame overflow
If a byte is received after a correct CRC, the buffer manager sets
RX_FRAME_OVERFLOW_STATUS in register HOSTIF_INT_STATUS_REG. No bytes
beyond the frame length limit are stored and the frame is discarded by not setting
HOSTIF_DATA_READY_STATUS_REG.RX<n>_DATA_READY. The corresponding
output will remain high until the firmware sets
RX_BUFFER_FRAME_OVERFLOW_CLR_STATUS in register
UM10858
User manual
COMPANY PUBLIC
1. The buffer manager can only clear bit
HOSTIF_DATA_READY_STATUS_REG.TX_DATA_READY.
2. Setting bit HOSTIF_SET_DATA_READY_REG.SET_TX_DATA_READY by the
firmware will only cause bit
HOSTIF_DATA_READY_STATUS_REG.TX_DATA_READY to be set if the
buffer manager is not using the TX buffer (bit
HOSTIF_STATUS_REGTX_BUFFER_LOCK is 0). Setting bit
HOSTIF_CLR_DATA_READY_REG.CLR_TX_DATA_READY by the firmware
will only cause bit HOSTIF_DATA_READY_STATUS_REG.TX_DATA_READY
to be cleared if the buffer manager is not using the TX buffer (bit
HOSTIF_STATUS_REGTX_BUFFER_LOCK is 0).
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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