Table of Contents
Advertisement
NXP Semiconductors
Step 2: Configure the I2C slave address with an APB Write Transaction using write data
0x0000002A at offset address 0x0000C {I2C_ADDRESS_REG}.
Step 3: Configure the I2C clock frequency with an APB Write Transaction using write
data 0x00000000 at offset address 0x00004 {BAUDRATE_REG}.
Step 4: Configure the byte count with an APB Write Transaction using write data
0x00000007 at offset address 0x00014 {BYTECOUNT_CONFIG_REG}.
Step 5: Enable the I2C Master reception with an APB Write Transaction using write data
0x00000001 at offset address 0x00020 {CONTROL_REG} & wait until the I2C reception
is completed.
Step 6: Read the I2C data received with an two APB Read Transaction at offset address
0x00050 - 0x0005C {RX_DATA}.
1. First APB Read Transaction using read data = {BYTE4, BYTE3, BYTE2, BYTE1}
2. Second APB Read Transaction using read data = {XX, BYTE7, BYTE6, BYTE5}
Note: In the Example, the interrupts are not considered & targeted for the explanation of
data integrity & the programming procedure for the I2C reception.
UM10858
User manual
COMPANY PUBLIC
Fig 47. I2C master receiver example
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
250 of 345
Advertisement
Table of Contents
