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14.1.5 Baud rate calculation
The SCL (serial clock line) frequency calculation is based on 27.12 MHz clock. The
BAUDRATE_REG register (see
transmissions. The SCL (serial clock) line frequency is determined as follows.
SCL
The baud rate parameter can be calculated using the following equation.
If
If
If
14.1.6 SDA_Hold calculation
The I2C-Bus specification requires a hold time for the SDA signal of at least 300 ns to
bridge the undefined region of the falling edge of SCL in Standard and Fast modes. This
300 ns hold time is computed based on the 27.12 MHz clock (27.12 MHz) and written to
the SDA_HOLD_REG register
The SDA hold requirements in Fast-mode Plus show that this 300 ns window is no longer
necessary to ensure a proper functionality of the controller. It is therefore recommended
to set the SDA_HOLD to 0x00 when operating in Fast-mode Plus, in order for the data to
change as early as possible after the falling edge of the SCL line.
Example:
If the SCL frequency is 339; then the BAUDRATE register bit field is 0x35.
So, the SDA_HOLD register bit field is would be:
Here, SDA_HOLD can be any integer value between 9 & 19.
Note:
UM10858
User manual
COMPANY PUBLIC
=
Frequency
+
27
BAUDRATE
BAUDRATE_REG = 0x00000000 then SCL frequency = 1MHz (1 Mbit/s)
BAUDRATE_REG = 0x00000029 then SCL frequency = 400kHz (400 kbit/s)
BAUDRATE_REG = 0x0000006D then SCL frequency = 100kHz to 100 kbit/s
0.3 x 27.12 < SDA_HOLD < (BAUDRATE / 2 - 0.25 x 27.12)
0.3 x 27.12 < SDA_HOLD < (0x35 / 2 - 0.25 x 27.12)
1. Setting the Value (Non-zero) for the SDA_HOLD register bit field is not
mandatory. If the SDA_HOLD register bit field is 0x0, then the I
internal take care of 300 ns hold time for I2C standard and fast modes
2. The SDA_HOLD register bit field is applicable only for I2C standard and fast
modes.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Table
277) controls the speed of the I2C bus
27
.
12
MHz
Examples:
(Table
278).
314514
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