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NXP Semiconductors
14.2 SPI Master Interface
The SPI is a 4-wire serial interface designed to interface with a large range of serial
peripheral or memory devices. The SPI master controller is one of two SPI controllers
supported by PN7462 family. The SPI slave controller is described in
14.2.1 SPI Master features
• Half-Duplex synchronous transfers
• Supports Motorola SPI frame formats only (SPI Block Guide V04.0114 (Freescale)
• Multiple data rates -1, 1.51, 2.09, 2.47, 3.01, 4.52, 5.42 and 6.78 Mbit/s
• Up to two Slave Select, with selectable polarity
• Programmable clock polarity and phase
• Supports 8-bit transfers only
• Maximum frame size: 511 data bytes payload + 1 CRC Byte
• AHB Master interface for data transfer
• Optional CRC calculation (1 byte) on all data of TX and RX buffer
14.2.2 General description
Fig 48
single slave can communicate on the bus during a given data transfer. Data transfers are
in principle full duplex, with frames of 4 bits to 16 bits of data flowing from the master to
the slave and from the slave to the master.
UM10858
User manual
COMPANY PUBLIC
specification)
shows the connection SPI master with two SPI slaves. Only a single master and a
Fig 48. Connection between SPI master and slaves
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Section
11.3.3.
© NXP B.V. 2018. All rights reserved.
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