NXP Semiconductors PN7462 series User Manual page 309

NXP Semiconductors
Bit
15
14:11
10:7
6
5
4
3:0
HOSTIF_INT_ENABLE_REG
This register is a collection of interrupt enable commands. Writing 1 to this register does
set the corresponding interrupt request enable flag. Writing 0 to this register has no
effect.
Table 351. HOSTIF_INT_ENABLE_REG (address offset 0x3FE4)
Bit
31:27
26
25
UM10858
User manual
COMPANY PUBLIC
Symbol Access
TX_TIMEOUT_STATU W
S
RX_FRAME_OVERFL W
OW_STATUS
RX_FRAME_UNDERF W
LOW_STATUS
TX_FRAME_NOT_AVAI W
LABLE_STATUS
RX_BUFFER_NOT_A W
VAILABLE_STATUS
EOT_STATUS W
EOR_STATUS W
Symbol Access
RESERVED W
HSU_RX_FER_ENABL W
E
BUFFER_CFG_CHAN W
GED_ERROR_ENABL
E
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Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset Description
Value
0 Inter-character timeout (TIC) exceeded on
transmitted frame interrupt status
0 0001 - Frame overflow interrupt status for
RX buffer 0
0010 - Frame overflow interrupt status for
RX buffer 1
0100 - Frame overflow interrupt status for
RX buffer 2
1000 - Frame overflow interrupt status for
RX buffer 3
0 0001 - Frame underflow interrupt status for
RX buffer 0
0010 - Frame underflow interrupt status for
RX buffer 1
0100 - Frame underflow interrupt status for
RX buffer 2
1000 - Frame underflow interrupt status for
RX buffer 3
0 HOSTIF_DATA_READY_STATUS_REG.T
X_DATA_READY=0 when Host read
request interrupt status
0 No receive buffers available interrupt status
0 EOT interrupt status
0 0001 - EOR interrupt status for RX buffer 0
0010 - EOR interrupt status for RX buffer 1
0100 - EOR interrupt status for RX buffer 2
1000 - EOR interrupt status for RX buffer 3
Reset
Description
Value
0 Reserved
0 HSU RX frame error interrupt enable
0 Buffer configuration changed during use
interrupt enable
UM10858
© NXP B.V. 2018. All rights reserved.
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