NXP Semiconductors PN7462 series User Manual page 331

NXP Semiconductors
Bit Symbol
7 TREG
31:8 RESERVED
15.4.2.14 USB endpoint toggle
Table 369. USB endpoint toggle (address offset = 0x34)
Reset value: 0x00000000
Bit Symbol
29:0 TOGGLE
31:30 RESERVED
15.4.2.15 USB internal PLL
Table 370. USB internal PLL (address offset = 0x38)
Reset value: 0x00000000
Bit Symbol
0 SEL_EXT_CLK
31:3 RESERVED
UM10858
User manual
COMPANY PUBLIC
Value Description
Toggle register available This indicates if the Data Toggle
debug register is reserved or not.
Reserved
Value Description
Endpoint data toggle: This field indicates the current value of
the data toggle for the corresponding endpoint.
Reserved
Value Description
Select external crystal clock.
Internal PLL and RC circuit is selected as input clock for the
0
USB block
External clock input pin is selected as input clock for USB
1
block. The input clock must be 48MHz in this case.
Reserved
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Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Reset
Value
Reset
Value
Reset
Value
0
0
© NXP B.V. 2018. All rights reserved.
Access
RO
RO
Access
RO
RO
Access
R/W
R/W
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