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NXP Semiconductors LPC1769 User Manual

NXP Semiconductors LPC1769 User Manual

Arm, arm cortex-m3, 32-bit, usb, ethernet, can, i2s, microcontroller

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UM10360

LPC176x/5x User manual

Rev. 3 — 20 December 2013

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LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763,

LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM

Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller

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LPC176x/5x user manual

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Page 1 LPC176x/5x User manual Rev. 3 — 20 December 2013 User manual Document information Info Content Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763, LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller Abstract LPC176x/5x user manual...
Page 2 UM10360 NXP Semiconductors LPC17xx user manual Revision history Date Description 20131220 LPC176x/5x user manual Modifications: • Part ID for part LPC1763 added. • Changed title to “LPC176x/5x User manual”. • Updated numbering for CAN interfaces: CAN1 uses SCC = 0, CAN2 uses SCC = 1. See Section 16.13 “ID look-up table RAM”...
Page 3 UM10360 NXP Semiconductors LPC17xx user manual Revision history …continued Date Description 20100104 LPC176x/5x user manual revision. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10360 All information provided in this document is subject to legal disclaimers.
Page 4: Chapter 1: Lpc176X/5X Introductory Information
High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU frequency. Other versions operate at up to an 100 MHz CPU frequency. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals.
Page 5: Features
• ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory Protection Unit (MPU) supporting eight regions is included. •...
Page 6 UM10360 NXP Semiconductors Chapter 1: LPC176x/5x Introductory information – I S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I S interface can be used with the GPDMA. The I S interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output.
Page 7: Applications
UM10360 NXP Semiconductors Chapter 1: LPC176x/5x Introductory information • Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).
Page 8: Ordering Information
UM10360 NXP Semiconductors Chapter 1: LPC176x/5x Introductory information 1.4 Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1769FBD100 LPC1768FBD100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm LQFP100 SOT407-1...
Page 9: Simplified Block Diagram
UM10360 NXP Semiconductors Chapter 1: LPC176x/5x Introductory information 1.5 Simplified block diagram Ethernet Trace JTAG Port interface interface interface Test/Debug Interface Clock Generation, Ethernet device, Clocks Power Control, 10/100 controller host, Brownout Detect, ARM Cortex-M3 Controls and other system functions...
Page 10: Architectural Overview
UM10360 NXP Semiconductors Chapter 1: LPC176x/5x Introductory information 1.6 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and D-code buses which are faster and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.
Page 11: Debug Related Options
UM10360 NXP Semiconductors Chapter 1: LPC176x/5x Introductory information Debug related options: • A JTAG debug interface is included. • Serial Wire Debug is included. Serial Wire Debug allows debug operations using only 2 wires, simple trace functions can be added with a third wire.
Page 12: Block Diagram
UM10360 NXP Semiconductors Chapter 1: LPC176x/5x Introductory information 1.10 Block diagram JTAG Ethernet PHY interface Debug Port interface interface clock generation, TEST/DEBUG clocks INTERFACE power control, Ethernet device, and other 10/100 controls controller host, system functions ARM Cortex-M3 internal voltage regulator...
Page 13: Chapter 2: Lpc176X/5X Memory Map
UM10360 Chapter 2: LPC176x/5x Memory map Rev. 3 — 19 December 2013 User manual 2.1 Memory map and peripheral addressing The ARM Cortex-M3 processor has a single 4 GB address space. The following table shows how this space is used on the LPC176x/5x. Table 3.
Page 14 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx APB1 peripherals LPC1768 memory space 0x4010 0000 4 GB 0xFFFF FFFF system control 0x400F C000 reserved 30 - 16 reserved 0x400C 0000...
Page 15: Apb Peripheral Addresses
UM10360 NXP Semiconductors Chapter 2: LPC176x/5x Memory map Figure 3 Table 4 show different views of the peripheral address space. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64 peripherals.
Page 16: Memory Re-Mapping
UM10360 NXP Semiconductors Chapter 2: LPC176x/5x Memory map Table 5. APB1 peripherals and base addresses APB1 peripheral Base address Peripheral name 0x4008 0000 reserved 0x4008 4000 reserved 0x4008 8000 SSP0 0x4008 C000 0x4009 0000 Timer 2 0x4009 4000 Timer 3...
Page 17 UM10360 NXP Semiconductors Chapter 2: LPC176x/5x Memory map For these areas, both attempted data access and instruction fetch generate an exception. In addition, a Bus Fault exception is generated for any instruction fetch that maps to an AHB or APB peripheral address.
Page 18: Chapter 3: Lpc176X/5X System Control
UM10360 Chapter 3: LPC176x/5x System control Rev. 3 — 19 December 2013 User manual 3.1 Introduction The system control block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include: •...
Page 19: Register Description
UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control 3.3 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 7. Summary of system control registers Name...
Page 20 UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control Reset to the external on-chip circuitry reset watchdog reset Reset to PCON.PD WAKE-UP TIMER START power-down COUNT 2 internal RC EINT0 wake-up oscillator EINT1 wake-up write “1” EINT2 wake-up from APB EINT3 wake-up...
Page 21 UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control starts stable IRC status RESET DD(REG)(3V3) valid threshold 60 μs 1 μs; IRC stability count boot time supply ramp-up time 7 μs 181 μs 224 μs user code processor status flash read...
Page 22: Reset Source Identification Register (Rsid - 0X400F C180)
UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control 3.4.1 Reset Source Identification Register (RSID - 0x400F C180) This register contains one bit for each source of Reset. Writing a 1 to any of these bits clears the corresponding read-side bit to 0. The interactions among the four sources are described below.
Page 23: Brown-Out Detection
UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control 3.5 Brown-out detection The LPC176x/5x includes a Brown-Out Detector (BOD) that provides 2-stage monitoring of the voltage on the V pins. If this voltage falls below the BOD interrupt trip DD(REG)(3V3) level (typically 2.2 V under nominal room temperature conditions), the BOD asserts an interrupt signal to the NVIC.
Page 24: External Interrupt Inputs
UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control 3.6 External interrupt inputs TheLPC176x/5x includes four External Interrupt Inputs as selectable pin functions. The logic of an individual external interrupt is represented in Figure 6. In addition, external interrupts have the ability to wake up the CPU from Power-down mode. Refer to Section 4.8.8 “Wake-up from Reduced Power Modes”...
Page 25: Register Description
UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control 3.6.1 Register description The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.
Page 26: 0X400F C148)
UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control Table 10. External Interrupt Flag register (EXTINT - address 0x400F C140) bit description Symbol Description Reset value EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state.
Page 27: 0X400F C14C)
UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control Table 11. External Interrupt Mode register (EXTMODE - address 0x400F C148) bit description Symbol Value Description Reset value EXTMODE0 Level-sensitivity is selected for EINT0. EINT0 is edge sensitive. EXTMODE1 Level-sensitivity is selected for EINT1.
Page 28 UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control Table 12. External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit description Symbol Value Description Reset value EXTPOLAR3 0 EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3). EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3).
Page 29: Other System Controls And Status Flags
UM10360 NXP Semiconductors Chapter 3: LPC176x/5x System control 3.7 Other system controls and status flags Some aspects of controlling LPC176x/5x operation that do not fit into peripheral or other registers are grouped here. 3.7.1 System Controls and Status register (SCS - 0x400F C1A0) The SCS register contains several control/status bits related to the main oscillator.
Page 30: Chapter 4: Lpc176X/5X Clocking And Power Control
UM10360 Chapter 4: LPC176x/5x Clocking and power control Rev. 3 — 19 December 2013 User manual 4.1 Summary of clocking and power control functions This section describes the generation of the various clocks needed by the LPC176x/5x and options of clock source selection, as well as power control and wake-up from reduced power modes.
Page 31: Register Description
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.2 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 14. Summary of system control registers...
Page 32: Oscillators
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.3 Oscillators The LPC176x/5x includes three independent oscillators. These are the Main Oscillator, the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. This can be seen in...
Page 33 UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control LPC17xx LPC17xx XTAL1 XTAL2 XTAL1 XTAL2 < = > Xtal Clock Fig 8. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for C evaluation Table 15.
Page 34: Rtc Oscillator
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register.
Page 35: Clock Source Selection Multiplexer
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.4 Clock source selection multiplexer Several clock sources may be chosen to drive PLL0 and ultimately the CPU and on-chip peripheral devices. The clock sources available are the main oscillator, the RTC oscillator, and the Internal RC oscillator.
Page 36: Pll0 (Phase Locked Loop 0)
PLL (see Section 4.6). PLL0 can produce a clock up to the maximum allowed for the CPU, which is 120 MHz on high speed versions (LPC1769 and LPC1759), and 100 MHz on other versions. 4.5.1 PLL0 operation The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value "N", which may be in the range of 1 to 256.
Page 37: Pll0 Register Description
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.5.2 PLL0 register description PLL0 is controlled by the registers shown in Table 18. More detailed descriptions follow. Warning: Improper setting of PLL0 values may result in incorrect operation of the device! Table 18.
Page 38: Pll0 Configuration Register (Pll0Cfg - 0X400F C084)
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control feed sequence has been given (see Section 4.5.8 “PLL0 Feed register (PLL0FEED - 0x400F C08C)”). Table 19. PLL Control register (PLL0CON - address 0x400F C080) bit description Symbol Description Reset...
Page 39: Pll0 Status Register (Pll0Stat - 0X400F C088)
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 21. Multiplier values for PLL0 with a 32 kHz input Multiplier Pre-divide Multiplier Pre-divide 4272 279.9698 12085 396.0013 4395 288.0307 12207 399.9990 4578 300.0238 12817 419.9875 4725 309.6576 12817 279.9916...
Page 40: Pll0 Interrupt: Plock0
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control proper PLL0 feed has occurred (see Section 4.5.8 “PLL0 Feed register (PLL0FEED - 0x400F C08C)”). Table 22. PLL Status register (PLL0STAT - address 0x400F C088) bit description Symbol Description Reset...
Page 41: Pll0 Feed Register (Pll0Feed - 0X400F C08C)
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 23. PLL control bit combinations PLLC0 PLLE0 PLL Function PLL0 is turned off and disconnected. PLL0 outputs the unmodified clock input. PLL0 is active, but not yet connected. PLL0 can be connected after PLOCK0 is asserted.
Page 42 UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 25. PLL frequency parameter Parameter Description the frequency of PLLCLKIN from the Clock Source Selection Multiplexer. the frequency of the PLLCLK (output of the PLL Current Controlled Oscillator) PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG NSEL0 field + 1).
Page 43: Procedure For Determining Pll0 Settings
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 26. Additional Multiplier Values for use with a Low Frequency Clock Input Low Frequency PLL Multipliers 4272 4395 4578 4725 4807 5127 5188 5400 5493 5859 6042 6075 6104...
Page 44: Examples Of Pll0 Settings
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.5.12 Examples of PLL0 settings The following table gives a summary of examples that illustrate selecting PLL0 values based on different system requirements. Table 27. Summary of PLL0 examples Example Description •...
Page 45: Example 3
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Example 2 Assumptions: • The USB interface will be used in the application and will be clocked from PLL0. • The desired CPU rate is 60 MHz. • An external 4 MHz crystal or clock source will be used as the system clock source.
Page 46 UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Example 3 Assumptions: • The USB interface will not be used in the application, or will be clocked by PLL1. • The desired CPU rate is 72 MHz • The 32.768 kHz RTC clock source will be used as the system clock source Calculations: ...
Page 47: Pll0 Setup Sequence
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.5.13 PLL0 setup sequence The following sequence must be followed step by step in order to have PLL0 initialized and running: 1. Disconnect PLL0 with one feed sequence if PLL0 is already connected.
Page 48: Pll1 (Phase Locked Loop 1)
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.6 PLL1 (Phase Locked Loop 1) PLL1 receives its clock input from the main oscillator only and can be used to provide a fixed 48 MHz clock only to the USB subsystem. This is an option in addition to the possibility of generating the USB clock from PLL0.
Page 49: C0A0)
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 29. PLL1 registers Name Description Access Reset Address value PLL1CFG PLL1 Configuration Register. Holding register 0x400F C0A4 for updating PLL1 configuration values. Values written to this register do not take effect until a valid PLL1 feed sequence has taken place.
Page 50: Pll1 Configuration Register (Pll1Cfg - 0X400F C0A4)
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 30. PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description Symbol Description Reset value PLLE1 PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency.
Page 51: Pll1 Modes
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 32. PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description Symbol Description Reset value MSEL1 Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1.
Page 52: Pll1 Feed Register
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC) A correct feed sequence must be written to the PLL1FEED register in order for changes to the PLL1CON and PLL1CFG registers to take effect. The feed sequence is: 1.
Page 53: Pll1 Frequency Calculation
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.6.8 PLL1 frequency calculation The PLL1 equations use the following parameters: Table 35. Elements determining PLL frequency Element Description the frequency from the crystal oscillator the frequency of the PLL1 current controlled oscillator...
Page 54 UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 36. PLL1 Divider values Values allowed for using PLL1 with USB are highlighted. PSEL1 Bits (PLL1CFG bits [6:5]) Value of P Table 37. PLL1 Multiplier values Values allowed for using PLL1 with USB are highlighted.
Page 55: Clock Dividers
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.7 Clock dividers The output of the PLL0 must be divided down for use by the CPU and the USB subsystem (if used with PLL0, see Section 4.6). Separate dividers are provided such that the CPU frequency can be determined independently from the USB subsystem, which always requires 48 MHz with a 50% duty cycle for proper operation.
Page 56: Usb Clock Configuration Register (Usbclkcfg - 0X400F C108)
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 38. CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit description Symbol Value Description Reset value CCLKSEL Selects the divide value for creating the CPU clock (CCLK) 0x00 from the PLL0 output.
Page 57: Peripheral Clock Selection Registers 0 And 1
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 39. USB Clock Configuration register (USBCLKCFG - address 0x400F C108) bit description Symbol Value Description Reset value USBSEL Selects the divide value for creating the USB clock from the PLL0 output.
Page 58 UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 41. Peripheral Clock Selection register 1 (PCLKSEL1 - address 0x400F C1AC) bit description Symbol Description Reset value PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface. PCLK_GPIOINT Peripheral clock selection for GPIO interrupts.
Page 59: Power Control
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.8 Power control The LPC176x/5x supports a variety of power control features: Sleep mode, Deep Sleep mode, Power-down mode, and Deep Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, re-configuring PLL values, and/or altering the CPU clock divider value.
Page 60: Power-Down Mode
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly all clocks are stopped, and the DSFLAG bit in PCON is set, see Table 44. The IRC remains running and can be configured to drive the Watchdog Timer, allowing the Watchdog to wake up the CPU.
Page 61: Deep Power-Down Mode
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.8.4 Deep Power-down mode In Deep Power-down mode, power is shut off to the entire chip with the exception of the Real-Time Clock, the RESET pin, the WIC, and the RTC backup registers. Entry to Deep...
Page 62: Power Mode Control Register (Pcon - 0X400F C0C0)
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.8.7 Power Mode Control register (PCON - 0x400F C0C0) Controls for some reduced power modes and other power related controls are contained in the PCON register, as described in Table Table 44.
Page 63: Encoding Of Reduced Power Modes
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.8.7.1 Encoding of Reduced Power Modes The PM1and PM0 bits in PCON allow entering reduced power modes as needed. The encoding of these bits allows backward compatibility with devices that previously only supported Sleep and Power-down modes.
Page 64 UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral.
Page 65: Power Control Usage Notes
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit description Symbol Description Reset value PCI2S S interface power/clock control bit. Reserved. PCGPDMA GPDMA function power/clock control bit.
Page 66: Wake-Up Timer
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.9 Wake-up timer The LPC176x/5x begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to begin quickly.
Page 67: External Clock Output Pin
UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control 4.10 External clock output pin For system test and development purposes, any one of several internal clocks may be brought out on the CLKOUT function available on the P1.27 pin, as shown in...
Page 68 UM10360 NXP Semiconductors Chapter 4: LPC176x/5x Clocking and power control Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description Symbol Value Description Reset value CLKOUTDIV Integer value to divide the output clock by, minus one. 0000 Clock is divided by 1.
Page 69: Chapter 5: Lpc176X/5X Flash Accelerator
UM10360 Chapter 5: LPC176x/5x Flash accelerator Rev. 3 — 19 December 2013 User manual 5.1 Introduction The flash accelerator block in the LPC176x/5x allows maximization of the performance of the Cortex-M3 processor when it is running code from flash memory, while also saving power.
Page 70: Flash Programming Issues
UM10360 NXP Semiconductors Chapter 5: LPC176x/5x Flash accelerator 5.2.2 Flash programming Issues Since the flash memory does not allow accesses during programming and erase operations, it is necessary for the flash accelerator to force the CPU to wait if a memory access to a flash address is requested while the flash memory is busy with a programming operation.
Page 71: Flash Accelerator Configuration Register
0100 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. 0101 Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions.
Page 72 UM10360 NXP Semiconductors Chapter 5: LPC176x/5x Flash accelerator If a flash instruction fetch and a flash data access from the CPU occur at the same time, the multilayer matrix gives precedence to the data access. This is because a stalled data access always slows down execution, while a stalled instruction fetch often does not.
Page 73: Chapter 6: Lpc176X/5X Nested Vectored Interrupt Controller (Nvic)
UM10360 Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) Rev. 3 — 19 December 2013 User manual 6.1 Features • Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3 • Tightly coupled interrupt controller provides low interrupt latency •...
Page 74 UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Interrupt Exception Vector Function Flag(s) Number Offset 0x40 Watchdog Interrupt (WDINT) 0x44 Timer 0 Match 0 - 1 (MR0, MR1)
Page 75 UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Interrupt Exception Vector Function Flag(s) Number Offset 0x78 SSP0 Tx FIFO half empty of SSP0 Rx FIFO half full of SSP0...
Page 76: Vector Table Remapping
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.4 Vector table remapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register (VTOR) contained in the Cortex-M3.
Page 77: Register Description
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5 Register description The following table summarizes the registers in the NVIC as implemented in the LPC176x/5x. The Cortex-M3 User Guide Section 34.4.2 provides a functional description of the NVIC.
Page 78: Interrupt Set-Enable Register 0 Register (Iser0 - 0Xe000 E100)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.1 Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100) The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are enabled via the ISER1...
Page 79: Interrupt Set-Enable Register 1 Register (Iser1 - 0Xe000 E104)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.2 Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104) The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling interrupts is done through the ICER0 and ICER1 registers (Section 6.5.3...
Page 80: Interrupt Clear-Enable Register 0 (Icer0 - 0Xe000 E180)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.3 Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180) The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are disabled via the ICER1...
Page 81: Interrupt Clear-Enable Register 1 Register (Icer1 - 0Xe000 E184)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.4 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) The ICER1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Enabling interrupts is done through the ISER0 and ISER1 registers (Section 6.5.1...
Page 82: Interrupt Set-Pending Register 0 Register (Ispr0 - 0Xe000 E200)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.5 Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200) The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their...
Page 83: Interrupt Set-Pending Register 1 Register (Ispr1 - 0Xe000 E204)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.6 Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204) The ISPR1 register allows setting the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers (Section 6.5.7...
Page 84: (Icpr0 - 0Xe000 E280)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.7 Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have...
Page 85: Interrupt Clear-Pending Register 1 Register
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.8 Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284) The ICPR1 register allows clearing the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6.5.5...
Page 86: Interrupt Active Bit Register 0 (Iabr0 - 0Xe000 E300)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.9 Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300) The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if they are enabled.
Page 87: Interrupt Active Bit Register 1 (Iabr1 - 0Xe000 E304)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.10 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304) The IABR1 register is a read-only register that allows reading the active state of the second group of peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if they are enabled.
Page 88: Interrupt Priority Register 0 (Ipr0 - 0Xe000 E400)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.11 Interrupt Priority Register 0 (IPR0 - 0xE000 E400) The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority.
Page 89: Interrupt Priority Register 3 (Ipr3 - 0Xe000 E40C)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority.
Page 90: Interrupt Priority Register 6 (Ipr6 - 0Xe000 E418)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.17 Interrupt Priority Register 6 (IPR6 - 0xE000 E418) The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority.
Page 91: Software Trigger Interrupt Register (Stir - 0Xe000 Ef00)
UM10360 NXP Semiconductors Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC) 6.5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00) The STIR register provides an alternate way for software to generate an interrupt, in addition to using the ISPR registers. This mechanism can only be used to generate peripheral interrupts, not system exceptions.
Page 92: Chapter 7: Lpc176X/5X Pin Configuration
UM10360 Chapter 7: LPC176x/5x Pin configuration Rev. 3 — 19 December 2013 User manual 7.1 LPC176x/5x pin configuration 002aad945_1 Fig 14. LPC176x LQFP100 pin configuration 002aae158 Fig 15. LPC175x LQFP80 pin configuration UM10360 All information provided in this document is subject to legal disclaimers. ©...
Page 93 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration ball A1 LPC1768FET100 index area 002aaf723 Transparent top view Fig 16. Pin configuration TFBGA100 package Table 72. Pin allocation table TFBGA100 package Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A...
Page 94 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 72. Pin allocation table TFBGA100 package …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol P0[23]/AD0[0]/ P4[29]/TX_MCLK/ P2[3]/PWM1[4]/ P2[6]/PCAP1[0]/ I2SRX_CLK/CAP3[0] MAT2[1]/RXD3 DCD1/TRACEDATA[2] RI1/TRACECLK P2[7]/RD2/RTS1 P2[8]/TD2/TXD2 Row F VREFN RTCX1 RESET P1[31]/SCK1/...
Page 95: Lpc176X/5X Pin Description
UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 72. Pin allocation table TFBGA100 package …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row J P0[28]/SCL0/ P0[27]/SDA0/ P0[29]/USB_D+ P1[19]/MCOA0/ USB_SCL USB_SDA USB_PPWR/ CAP1[1] P1[22]/MCOB0/ P1[28]/MCOA2/ P0[1]/TD1/RXD3/SCL1 USB_PWRD/ PCAP1[0]/ MAT1[0]...
Page 96 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description Symbol LQFP LQFP Type Description P0[0] to P0[31] Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block.
Page 97 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description …continued Symbol LQFP LQFP Type Description P0[8] / I2STX_WS / P0[8] — General purpose digital input/output pin. MISO1 / MAT2[2] I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave.
Page 98 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description …continued Symbol LQFP LQFP Type Description P0[20] / DTR1 / P0[20] — General purpose digital input/output pin. SCL1 DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.
Page 99 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description …continued Symbol LQFP LQFP Type Description P0[28] / SCL0 / P0[28] — General purpose digital input/output pin. Open-drain 5 V tolerant USB_SCL digital I/O pad, compatible with I C-bus specifications for 100 kHz standard mode, 400 kHz Fast Mode, and 1 MHz Fast Mode Plus.
Page 100 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description …continued Symbol LQFP LQFP Type Description P1[18] / P1[18] — General purpose digital input/output pin. USB_UP_LED / USB_UP_LED — USB GoodLink LED indicator. It is LOW when device is PWM1[1] / CAP1[0] configured (non-control endpoints enabled).
Page 101 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description …continued Symbol LQFP LQFP Type Description P1[27] / CLKOUT / P1[27] — General purpose digital input/output pin. USB_OVRCR / CLKOUT — Clock output pin. CAP0[1] USB_OVRCR — USB port Over-Current status.
Page 102 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description …continued Symbol LQFP LQFP Type Description P2[4] / PWM1[5] / P2[4] — General purpose digital input/output pin. DSR1 / PWM1[5] — Pulse Width Modulator 1, channel 5 output.
Page 103 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description …continued Symbol LQFP LQFP Type Description P2[12] / EINT2 / P2[12] — General purpose digital input/output pin. 5 V tolerant pad with 5 I2STX_WS ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
Page 104 UM10360 NXP Semiconductors Chapter 7: LPC176x/5x Pin configuration Table 73. Pin description …continued Symbol LQFP LQFP Type Description RSTOUT RSTOUT — This is a 3.3 V pin. A LOW output on this pin indicates that the device is in the reset state, for any reason. This reflects the RESET input pin and all internal reset sources.
Page 105: Chapter 8: Lpc176X/5X Pin Connect Block
LPC176x/5x UM10360 Chapter 8: LPC176x/5x Pin connect block Rev. 3 — 19 December 2013 User manual 8.1 How to read this chapter Table 74 shows the functions of the PINSEL registers in the LPC176x/5x. Table 74. Summary of PINSEL registers Register Controls Table...
Page 106: Multiple Connections
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block Table 75. Pin function select register bits PINSEL0 to Function Value after Reset PINSEL9 Values Primary (default) function, typically GPIO port First alternate function Second alternate function Third alternate function The direction control bit in the GPIO registers is effective only when the GPIO function is selected for a pin.
Page 107: Function Of Pinmode In Open Drain Mode
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block The PINMODE_OD registers control the open drain mode for ports. The open drain mode causes the pin to be pulled low normally if it is configured as an output and the data value is 0.
Page 108: Register Description
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block 8.5 Register description The Pin Control Module contains 11 registers as shown in Table 78 below. Table 78. Pin Connect Block Register Map Name Description Access Reset Address Value PINSEL0 Pin function select register 0.
Page 109: Pin Function Select Register 0 (Pinsel0 - 0X4002 C000)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block 8.5.1 Pin Function Select register 0 (PINSEL0 - 0x4002 C000) The PINSEL0 register controls the functions of the lower half of Port 0. The direction control bit in FIO0DIR register is effective only when the GPIO function is selected for a pin.
Page 110: Pin Function Select Register 2 (Pinsel2 - 0X4002 C008)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block Table 80. Pin function select register 1 (PINSEL1 - address 0x4002 C004) bit description …continued PINSEL1 Pin name Function when Function Function Function Reset when 01 when 10 when 11 value...
Page 111: Pin Function Select Register 4 (Pinsel4 - 0X4002 C010)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block Table 82. Pin function select register 3 (PINSEL3 - address 0x4002 C00C) bit description …continued PINSEL3 Pin Function when Function when Function Function Reset name when 10 when 11 value 11:10 P1.21...
Page 112: Pin Function Select Register 7 (Pinsel7 - 0X4002 C01C)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block 8.5.6 Pin Function Select Register 7 (PINSEL7 - 0x4002 C01C) The PINSEL7 register controls the functions of the upper half of Port 3. The direction control bit in the FIO3DIR register is effective only when the GPIO function is selected for a pin.
Page 113: Pin Mode Select Register 0 (Pinmode0 - 0X4002 C040)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block 8.5.9 Pin Mode select register 0 (PINMODE0 - 0x4002 C040) This register controls pull-up/pull-down resistor configuration for Port 0 pins 0 to 15. Table 87. Pin Mode select register 0 (PINMODE0 - address 0x4002 C040) bit description...
Page 114: Pin Mode Select Register 2 (Pinmode2 - 0X4002 C048)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block Table 88. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description PINMODE1 Symbol Description Reset value 21:20 P0.26MODE Port 1 pin 26 control, see P0.00MODE. 29:22 Reserved. 31:30 Reserved.
Page 115: Pin Mode Select Register 4 (Pinmode4 - 0X4002 C050)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block Table 90. Pin Mode select register 3 (PINMODE3 - address 0x4002 C04C) bit description PINMODE3 Symbol Description Reset value 15:14 P1.23MODE Port 1 pin 23 control, see P0.00MODE. 17:16 P1.24MODE Port 1 pin 24 control, see P0.00MODE.
Page 116: Pin Mode Select Register 7 (Pinmode7 - 0X4002 C05C)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block 8.5.14 Pin Mode select register 7 (PINMODE7 - 0x4002 C05C) This register controls pull-up/pull-down resistor configuration for Port 3 pins 16 to 31. For details see Section 8.4 “Pin mode select register values”.
Page 117: Open Drain Pin Mode Select Register
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block Table 94. Open Drain Pin Mode select register 0 (PINMODE_OD0 - address 0x4002 C068) bit description …continued PINMODE Symbol Value Description Reset _OD0 value P0.10OD Port 0 pin 10 open drain mode control, see P0.00OD P0.11OD...
Page 118: Open Drain Pin Mode Select Register 2 (Pinmode_Od2 - 0X4002 C070)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block Table 95. Open Drain Pin Mode select register 1 (PINMODE_OD1 - address 0x4002 C06C) bit description …continued PINMODE Symbol Value Description Reset _OD1 value Reserved. P1.08OD Port 1 pin 8 open drain mode control, see P1.00OD P1.09OD...
Page 119: Open Drain Pin Mode Select Register 3 (Pinmode_Od3 - 0X4002 C074)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block Table 96. Open Drain Pin Mode select register 2 (PINMODE_OD2 - address 0x4002 C070) bit description …continued PINMODE Symbol Value Description Reset _OD2 value P2.05OD Port 2 pin 5 open drain mode control, see P2.00OD P2.06OD...
Page 120: C Pin Configuration Register (I2Cpadcfg - 0X4002 C07C)
UM10360 NXP Semiconductors Chapter 8: LPC176x/5x Pin connect block Table 98. Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit description …continued PINMODE Symbol Value Description Reset _OD4 value P4.28OD Port 4 pin 28 open drain mode control.
Page 121: Basic Configuration
UM10360 Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Rev. 3 — 19 December 2013 User manual 9.1 Basic configuration GPIOs are configured using the following registers: 1. Power: always enabled. 2. Pins: See Section 8.3 for GPIO pins and their modes. 3.
Page 122: Applications
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) • Registers provide a software view of pending rising edge interrupts, pending falling edge interrupts, and overall pending GPIO interrupts. • GPIO0 and GPIO2 interrupts share the same position in the NVIC with External Interrupt 3.
Page 123: Register Description
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5 Register description Due to compatibility requirements with the LPC2300 series ARM7-based products, the LPC176x/5x implements portions of five 32-bit General Purpose I/O ports. Details on a specific GPIO port usage can be found in Section 8.3.
Page 124: Gpio Port Direction Register Fioxdir (Fio0Dir To Fio4Dir- 0X2009 C000 To 0X2009 C080)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 102. GPIO interrupt register map Generic Description Access Reset PORTn Register Name value Name & Address IntEnR GPIO Interrupt Enable for Rising edge. IO0IntEnR - 0x4002 8090 IO2IntEnR - 0x4002 80B0 IntEnF GPIO Interrupt Enable for Falling edge.
Page 125: Gpio Port Output Set Register Fioxset (Fio0Set To Fio4Set - 0X2009 C018 To 0X2009 C098)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 104. Fast GPIO port Direction control byte and half-word accessible register description Generic Description Register Reset PORTn Register Register length (bits) value Address & Name name & access FIOxDIR0...
Page 126 UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Access to a port pin via the FIOxSET register is conditioned by the corresponding bit of the FIOxMASK register (see Section 9.5.5). Table 105. Fast GPIO port output Set register (FIO0SET to FIO4SET - addresses 0x2009 C018...
Page 127: Gpio Port Output Clear Register Fioxclr (Fio0Clr To Fio4Clr- 0X2009 C01C To 0X2009 C09C)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR- 0x2009 C01C to 0x2009 C09C) This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode.
Page 128: Gpio Port Pin Value Register Fioxpin (Fio0Pin To Fio4Pin- 0X2009 C014 To 0X2009 C094)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 108. Fast GPIO port output Clear byte and half-word accessible register description …continued Generic Description Register Reset PORTn Register Register length (bits) value Address & Name name & access...
Page 129 UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Only pins masked with zeros in the Mask register (see Section 9.5.5) will be correlated to the current content of the Fast GPIO port pin value register. Table 109. Fast GPIO port Pin value register (FIO0PIN to FIO4PIN- addresses 0x2009 C014 to...
Page 130: Fast Gpio Port Mask Register Fioxmask (Fio0Mask To Fio4Mask - 0X2009 C010 To 0X2009 C090)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 110. Fast GPIO port Pin value byte and half-word accessible register description …continued Generic Description Register Reset PORTn Register Register length (bits) value Address & Name name & access...
Page 131 UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Aside from the 32-bit long and word only accessible FIOxMASK register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 112, too. Next to providing the same functions as the FIOxMASK register, these additional registers allow easier and faster access to the physical port pins.
Page 132: Gpio Interrupt Registers
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5.6 GPIO interrupt registers The following registers configure the pins of Port 0 and Port 2 to generate interrupts. 9.5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080) This read-only register indicates the presence of interrupt pending on all of the GPIO ports that support GPIO interrupts.
Page 133: Gpio Interrupt Enable For Port 2 Rising Edge (Io2Intenr - 0X4002 80B0)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 114. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit description …continued Symbol Value Description Reset value P0.17ER Enable rising edge interrupt for P0.17. P0.18ER Enable rising edge interrupt for P0.18.
Page 134: Gpio Interrupt Enable For Port 0 Falling Edge (Io0Intenf - 0X4002 8094)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 115. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit description …continued Symbol Value Description Reset value P2.12ER Enable rising edge interrupt for P2.12. P2.13ER Enable rising edge interrupt for P2.13.
Page 135: Gpio Interrupt Enable For Port 2 Falling Edge (Io2Intenf - 0X4002 80B4)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 116. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094) bit description …continued Symbol Value Description Reset value P0.28EF Enable falling edge interrupt for P0.28.
Page 136: Gpio Interrupt Status For Port 0 Rising Edge Interrupt (Io0Intstatr - 0X4002 8084)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5.6.6 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) Each bit in these read-only registers indicates the rising edge interrupt status for port 0. Table 118. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084)
Page 137: Gpio Interrupt Status For Port 2 Rising Edge Interrupt (Io2Intstatr - 0X4002 80A4)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.5.6.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) Each bit in these read-only registers indicates the rising edge interrupt status for port 2. Table 119. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4)
Page 138: Gpio Interrupt Status For Port 2 Falling Edge Interrupt (Io2Intstatf - 0X4002 80A8)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 120. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) bit description …continued Symbol Value Description Reset value P0.8FEI Status of Falling Edge Interrupt for P0.8.
Page 139: Gpio Interrupt Clear Register For Port 0 (Io0Intclr - 0X4002 808C)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 121. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) bit description …continued Symbol Value Description Reset value P2.7FEI Status of Falling Edge Interrupt for P2.7.
Page 140: Gpio Interrupt Clear Register For Port 2 (Io2Intclr - 0X4002 80Ac)
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description …continued Symbol Value Description Reset value P0.22CI Clear GPIO port Interrupts for P0.22. P0.23CI Clear GPIO port Interrupts for P0.23.
Page 141: Gpio Usage Notes
UM10360 NXP Semiconductors Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO) 9.6 GPIO usage notes 9.6.1 Example: An instantaneous output of 0s and 1s on a GPIO port Solution 1: using 32-bit (word) accessible fast GPIO registers FIO0MASK = 0xFFFF00FF ;...
Page 142: Chapter 10: Lpc176X/5X Ethernet
UM10360 Chapter 10: LPC176x/5x Ethernet Rev. 3 — 19 December 2013 User manual 10.1 Basic configuration The Ethernet controller is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCENET. Remark: On reset, the Ethernet block is disabled (PCENET = 0). 2.
Page 143: Features
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 124. Ethernet acronyms, abbreviations, and definitions …continued Acronym or Definition Abbreviation Frame An Ethernet frame consists of destination address, source address, length type field, payload and frame check sequence. Half-word 16-bit entity...
Page 144: Architecture And Operation
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision backoff and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter.
Page 145: Dma Engine Functions
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet – The transmit DMA manager which reads descriptors and data from memory and writes status to memory. – The transmit retry module handling Ethernet retry and abort situations. – The transmit flow control module which can insert Ethernet pause frames.
Page 146: Ethernet Packet
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incoming data. Driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer.
Page 147: Overview
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet The Ethernet frame consists of the destination address, the source address, an optional VLAN field, the length/type field, the payload and the frame check sequence. Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred starting with the least significant bit.
Page 148: Example Phy Devices
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block. Receive flow control frames are automatically handled by the MAC. Transmit flow control frames can be initiated by software. In half duplex mode, the flow control module will generate back pressure by sending out continuous preamble only, interrupted by pauses to prevent the jabber limit from being exceeded.
Page 149: Registers And Software Interface
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.10 Registers and software interface The software interface of the Ethernet block consists of a register view and the format definitions for the transmit and receive descriptors. These two aspects are addressed in the next two subsections.
Page 150 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 128. Ethernet register definitions …continued Name Description Access Reset Value Address Status Status register. 0x5000 0104 RxDescriptor Receive descriptor base address register. 0x5000 0108 RxStatus Receive status base address register. 0x5000 010C RxDescriptorNumber Receive number of descriptors register.
Page 151: Ethernet Mac Register Definitions
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.11 Ethernet MAC register definitions This section defines the bits in the individual registers of the Ethernet block register map. 10.11.1 MAC Configuration Register 1 (MAC1 - 0x5000 0000) The MAC configuration register 1 (MAC1) has an address of 0x5000 0000. Its bit...
Page 152 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 130. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description Symbol Function Reset value FULL-DUPLEX When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode.
Page 153: Back-To-Back Inter-Packet-Gap Register (Ipgt - 0X5000 0008)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 131. Pad operation Type Auto detect VLAN pad Pad/CRC Action pad enable enable enable MAC2 [7] MAC2 [6] MAC2 [5] No pad or CRC check Pad to 60 bytes, append CRC Pad to 64 bytes, append CRC If untagged, pad to 60 bytes and append CRC.
Page 154: Collision Window / Retry Register (Clrt - 0X5000 0010)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.11.5 Collision Window / Retry Register (CLRT - 0x5000 0010) The Collision window / Retry register (CLRT) has an address of 0x5000 0010. Its bit definition is shown in Table 134. Table 134. Collision Window / Retry register (CLRT - address 0x5000 0010) bit description...
Page 155: Mii Mgmt Configuration Register (Mcfg - 0X5000 0020)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 137. Test register (TEST - address 0x5000 ) bit description Symbol Function Reset value SHORTCUT PAUSE This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. QUANTA TEST PAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received.
Page 156: Mii Mgmt Command Register
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 139. Clock select encoding Clock Select Bit 5 Bit 4 Bit 3 Bit 2 Maximum AHB clock supported Host Clock divided by 48 Host Clock divided by 52 Host Clock divided by 56...
Page 157: Mii Mgmt Read Data Register
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 142. MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description Symbol Function Reset value 15:0 WRITE When written, an MII Mgmt write cycle is performed using the 16-bit DATA data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR).
Page 158: Station Address 0 Register
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 3. Wait for busy bit to be cleared in MIND 4. Write 0 to MCMD 5. Read data from MRDD 10.11.15 Station Address 0 Register (SA0 - 0x5000 0040) The Station Address 0 register (SA0) has an address of 0x5000 0040. The bit definition of...
Page 159: Control Register Definitions
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to Figure 10.12 Control register definitions 10.12.1 Command Register (Command - 0x5000 0100) The Command register (Command) register has an address of 0x5000 0100.
Page 160: Receive Descriptor Base Address Register (Rxdescriptor - 0X5000 0108)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet • It is enabled and the Rx/TxEnable bit is set in the Command register or it just got disabled while still transmitting or receiving a frame. • Also, for the transmit channel, the transmit queue is not empty i.e.
Page 161: Receive Produce Index Register (Rxproduceindex - 0X5000 0114)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 152. Receive Number of Descriptors register (RxDescriptor - address 0x5000 0110) bit description Symbol Function Reset value 15:0 RxDescriptorNumber Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded.
Page 162: Transmit Descriptor Base Address Register (Txdescriptor - 0X5000 011C)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error. 10.12.8 Transmit Descriptor Base Address Register (TxDescriptor -...
Page 163: Transmit Produce Index Register (Txproduceindex - 0X5000 0128)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet The transmit number of descriptors register defines the number of descriptors in the descriptor array for which TxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7.
Page 164: Transmit Status Vector 1 Register
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet distributed over two registers TSV0 and TSV1. These registers are provided for debug purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted.
Page 165: Receive Status Vector Register
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted.Table 161...
Page 166: Flow Control Counter Register (Flowcontrolcounter - 0X5000 0170)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 162. Receive Status Vector register (RSV - address 0x5000 0160) bit description …continued Symbol Function Reset value Dribble Nibble Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out.
Page 167: Receive Filter Register Definitions
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.13 Receive filter register definitions 10.13.1 Receive Filter Control Register (RxFilterCtrl - 0x5000 0200) The Receive Filter Control register (RxFilterCtrl) has an address of 0x5000 0200. Table 165 lists the definition of the individual bits in the register.
Page 168: Receive Filter Wol Clear Register (Rxfilterwolclear - 0X5000 0208)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 166. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit description …continued Symbol Function Reset value Unused RxFilterWoL When the value is ’1’, the receive filter caused WoL. MagicPacketWoL When the value is ’1’, the magic packet filter caused WoL.
Page 169: Hash Filter Table Msbs Register
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.13.5 Hash Filter Table MSBs Register (HashFilterH - 0x5000 0214) The Hash Filter table MSBs register (HashFilterH) has an address of 0x5000 0214. Table 169 lists the bit definitions of the register. Details of Hash filter table use can be found in Section 10.17.10 “Receive filtering”...
Page 170: Interrupt Enable Register
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet The interrupt status register is read-only. Setting can be done via the IntSet register. Reset can be accomplished via the IntClear register. 10.14.2 Interrupt Enable Register (IntEnable - 0x5000 0FE4) The Interrupt Enable register (IntEnable) has an address of 0x5000 0FE4. The interrupt...
Page 171: Interrupt Set Register (Intset - 0X5000 0Fec)
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 172. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description Symbol Function Reset value RxOverrunIntClr Writing a ’1’ to one of these bits clears (0 to 7) the corresponding status bit in interrupt status register RxErrorIntClr IntStatus.
Page 172: Power-Down Register
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.14.5 Power-Down Register (PowerDown - 0x5000 0FF4) The Power-Down register (PowerDown) is used to block all AHB accesses except accesses to the Power-Down register. The register has an address of 0x5000 0FF4. The...
Page 173: Descriptor And Status Formats
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.15 Descriptor and status formats This section defines the descriptor format for the transmit and receive scatter/gather DMA engines. Each Ethernet frame can consist of one or more fragments. Each fragment corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for receive) and gather (for transmit) multiple fragments for a single Ethernet frame.
Page 174 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet received. The RxConsumeIndex is programmed by software and is the index of the next descriptor that the software receive driver is going to process. When RxProduceIndex == RxConsumeIndex, the receive buffer is empty. When RxProduceIndex ==...
Page 175 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Table 178. Receive Status HashCRC Word Symbol Description SAHashCRC Hash CRC calculated from the source address. 15:9 Unused 24:16 DAHashCRC Hash CRC calculated from the destination address. 31:25 - Unused The StatusInfo word contains flags returned by the MAC and flags generated by the receive data path reflecting the status of the reception.
Page 176: Transmit Descriptors And Statuses
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range"...
Page 177 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that will be used next by hardware and software. Both register act as counters starting at 0 and wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex contains the index of the next descriptor that is going to be filled by the software driver.
Page 178: Ethernet Block Functional Description
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet The transmit status consists of one word which is the StatusInfo word. It contains flags returned by the MAC and flags generated by the transmit data path reflecting the status of the transmission.
Page 179: Ahb Interface
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet To transmit a packet the software driver has to set up the appropriate Control registers and a descriptor to point to the packet data buffer before transferring the packet to hardware by incrementing the TxProduceIndex register. After transmission, hardware will increment TxConsumeIndex and optionally generate an interrupt.
Page 180 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet The Ethernet block includes two DMA managers. The DMA managers make it possible to transfer frames directly to and from memory with little support from the processor and without the need to trigger an interrupt for each frame.
Page 181 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet the one at the next higher, adjacent memory address. Wrap around means that when the Ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descriptor/status it reads/writes is the first descriptor/status of the array at the base address of the array.
Page 182: Initialization
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory.
Page 183: Transmit Process
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Please note that the transmit descriptors, receive descriptors and receive statuses are 8 bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit statuses need to be aligned on 4 byte boundaries; receive status arrays need to be aligned on 8 byte boundaries.
Page 184 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet After writing the descriptor the descriptor needs to be handed over to the hardware by incrementing (and possibly wrapping) the TxProduceIndex register. If the transmit data path is disabled, the device driver should not forget to enable the transmit data path by setting the TxEnable bit in the Command register.
Page 185 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection. When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1, this indicates the last fragment of the frame and thus the end of the frame is found.
Page 186 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet The transmission can generate several types of errors: LateCollision, ExcessiveCollision, ExcessiveDefer, Underrun, and NoDescriptor. All have corresponding bits in the transmission StatusInfo word. In addition to the separate bits in the StatusInfo word, LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error bit of the Status.
Page 187 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet • In the case of a transmission error (LateCollision, ExcessiveCollision, or ExcessiveDefer) or a multi-fragment frame where the device driver did provide the initial fragments but did not provide the rest of the fragments (NoDescriptor) or in the case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus register.
Page 188 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet boundary. Since the number of descriptors matches the number of statuses the status array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address boundary. The device driver writes the base address of the descriptor array (0x2008 10EC) to the TxDescriptor register and the base address of the status array (0x2008 11F8) to the TxStatus register.
Page 189: Receive Process
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet After transmitting each fragment of the frame the Tx DMA will write the status of the fragment’s transmission. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection.
Page 190 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Rx DMA manager reads Rx descriptor arrays When the RxEnable bit in the Command register is set, the Rx DMA manager reads the descriptors from memory at the address determined by RxDescriptor and RxProduceIndex.
Page 191 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet If the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame reception, error flags (Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or CRCError) are set in StatusInfo.
Page 192 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet receive errors cannot be reported in the receiver Status arrays which corrupts the hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The RxReset bit in the Command register should be used to soft reset the hardware.
Page 193 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet RxDescriptor RxStatus 0x200810EC 0x200811F8 FRAGMENT 0 BUFFER (8 bytes) 0x 2008 11F8 StatusInfo 0x200810EC PACKET 0x20081409 StatusHashCRC StatusInfo 0x 2008 1200 0x200810F0 CONTROL StatusHashCRC FRAGMENT 1 BUFFER (8 bytes) 0x200810F4 StatusInfo PACKET 0x 2008 1208...
Page 194 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet continuous memory space; even when a frame is distributed over multiple fragments it will typically be in a linear, continuous memory space; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space.
Page 195: Transmission Retry
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Each four pairs of bits transferred on the RMII interface are transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and buffer modules.
Page 196: Duplex Modes
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.17.7 Duplex modes The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex mode needs to be configured by the device driver software during initialization. For a full duplex connection the FullDuplex bit of the Command register needs to be set to 1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1;...
Page 197 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the Command register will start a pause frame transmission. The value inserted into the pause-timer value field of transmitted pause frames is programmed via the PauseTimer[15:0] bits in the FlowControlCounter register.
Page 198: Half-Duplex Mode Backpressure
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet device driver PauseTimer clear register MirrorCounter TxFlowCtl TxFlowCtl writes pause control pause control pause control RMII normal frame normal transimisson frame frame transmit transmission transmission transmission transmission MirrorCounter (1/515 bit slots) RMII pause in effect...
Page 199: Receive Filtering
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.17.10 Receive filtering Features of receive filtering The Ethernet MAC has several receive packet filtering functions that can be configured from the software driver: • Perfect address filter: allows packets with a perfectly matching station address to be identified and passed to the software driver.
Page 200 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet packet AcceptUnicastEn AcceptMulticastEn StationAddress IMPERFECT PERFECT AcceptMulticastHashEn HASH ADDRESS AcceptPerfectEn FILTER FILTER AcceptUnicastHashEn HashFilter FMatch RxFilterWoL RxFilterEnWoL RxAbort FReady Fig 24. Receive filter block diagram Unicast, broadcast and multicast Generic filtering based on the type of frame (unicast, multicast or broadcast) can be programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bits of the RxFilterCtrl register.
Page 201: Power Management
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet • Hash function: – The standard Ethernet cyclic redundancy check (CRC) function is calculated from the 6 byte destination address in the Ethernet frame (this CRC is calculated anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of the 32-bit CRC result are taken to form the hash.
Page 202 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet The Ethernet block supports power management with remote wake-up over LAN. The host system can be powered down, even including part of the Ethernet block itself, while the Ethernet block continues to listen to packets on the LAN. Appropriately formed packets can be received and recognized by the Ethernet block and used to trigger the host system to wake up from its power-down state.
Page 203: Enabling And Disabling Receive And Transmit
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all packets for a matching address, not just the Magic Packets i.e.
Page 204 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet ACTIVE RxStatus = 1 xxxxxxxxxxxxxxxxxx RxEnable = 0 and not busy receiving RxEnable = 1 RxProduceIndex = RxConsumeIndex - 1 INACTIVE RxStatus = 0 reset Fig 25. Receive Active/Inactive state machine After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is set in the Command register, the state machine transitions to the ACTIVE state.
Page 205: Transmission Padding And Crc
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet ACTIVE TxStatus = 1 xxxxxxxxxxxxxxxxxxxxxx TxEnable = 1 TxEnable = 0 and not busy transmitting TxProduceIndex <> TxConsumeIndex TxProduceIndex = TxConsumeIndex INACTIVE TxStatus = 0 reset Fig 26. Transmit Active/Inactive state machine After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set in the Command register and the Produce and Consume indices are not equal, the state machine transitions to the ACTIVE state.
Page 206: Huge Frames And Frame Length Checking
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet If EPADEN is 1, then small frames will be padded and a CRC will always be added to the padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be padded to 60 bytes and a CRC will be added creating 64 bytes frames;...
Page 207: Reset
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.17.18 Reset The Ethernet block has a hard reset input which is connected to the chip reset, as well as several soft resets which can be activated by setting the appropriate bit(s) in registers. All registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise specified.
Page 208: Ethernet Errors
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet • RegReset: Resets all of the data paths and registers in the host registers module, excluding the registers in the MAC. A soft reset of the registers will also abort all AHB transactions of the transmit and receive data path. The reset bit will be cleared autonomously by the Ethernet block.
Page 209: Ahb Bandwidth
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.18 AHB bandwidth The Ethernet block is connected to an AHB bus which must carry all of the data and control information associated with all Ethernet traffic in addition to the CPU accesses required to operate the Ethernet block and deal with message contents.
Page 210: Types Of Cpu Access
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet • Rx status write: – Receive status occupies 2 words (8 bytes) of memory and is written once for each use of a descriptor. – Two word write happens once every 64 bytes (16 words) of received data.
Page 211 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet for Ethernet traffic during simultaneous transmit and receive operations. This shows that it is not necessary to use the maximum CPU frequency for the Ethernet to work with plenty of bandwidth headroom. UM10360 All information provided in this document is subject to legal disclaimers.
Page 212: Crc Calculation
UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet 10.19 CRC calculation The calculation is used for several purposes: • Generation the FCS at the end of the Ethernet frame. • Generation of the hash table index for the hash table filtering.
Page 213 UM10360 NXP Semiconductors Chapter 10: LPC176x/5x Ethernet For hash filtering, this function is passed a pointer to the destination address part of the frame and the CRC is only calculated on the 6 address bytes. The hash filter uses bits [28:23] for indexing the 64-bits { HashFilterH, HashFilterL } vector.
Page 214: How To Read This Chapter
UM10360 Chapter 11: LPC176x/5x USB device controller Rev. 3 — 19 December 2013 User manual 11.1 How to read this chapter This chapter describes the USB controller which is present on all LPC176x/5x devices except the LPC1767. On some LPC176x/5x family devices, the USB controller can also be configured for Host or OTG operation.
Page 215: Features
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 184. USB related acronyms, abbreviations, and definitions used in this chapter Acronym/abbreviation Description Advanced High-performance bus ATLE Auto Transfer Length Extraction Analog Transceiver DMA Descriptor DMA Description Pointer Direct Memory Access...
Page 216: Functional Description
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 185. Fixed endpoint configuration Logical Physical Endpoint type Direction Packet size (bytes) Double buffer endpoint endpoint Control 8, 16, 32, 64 Control 8, 16, 32, 64 Interrupt 1 to 64...
Page 217: Analog Transceiver
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller MASTER USB_CONNECT INTERFACE ENGINE DMA interface (AHB master) USB_D+ EP_RAM SERIAL REGISTER ACCESS INTERFACE INTERFACE CONTROL ENGINE USB_D- USB_UP_LED register EP_RAM interface (4K) (AHB slave) USB DEVICE BLOCK Fig 27. USB device controller block diagram 11.6.1 Analog transceiver...
Page 218: Dma Engine And Bus Master Interface
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.6.5 DMA engine and bus master interface When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all endpoints.
Page 219: Pin Description
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Once data has been received or sent, the endpoint buffer can be read or written. How this is accomplished depends on the endpoint’s type and operating mode. The two operating modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode.
Page 220: Power Management Support
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 187. USB device controller clock sources Clock source Description AHB master clock Clock for the AHB master bus interface and DMA AHB slave clock Clock for the AHB slave interface...
Page 221: Remote Wake-Up
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.9.4 Remote wake-up The USB device controller supports software initiated remote wake-up. Remote wake-up involves resume signaling on the USB bus initiated from the device. This is done by clearing the SUS bit in the SIE Set Device Status register. Before writing into the register, all the clocks to the device controller have to be enabled using the USBClkCtrl register.
Page 222: Clock Control Registers
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 188. USB device register map …continued Name Description Access Reset value Address DMA registers USBDMARSt USB DMA Request Status 0x5000 C250 USBDMARClr USB DMA Request Clear 0x5000 C254 USBDMARSet USB DMA Request Set...
Page 223: Usb Clock Status Register
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 189. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description …continued Symbol Description Reset value Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 224: Usb Device Interrupt Status Register
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 191. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description …continued Symbol Description Reset value USB_NEED_CLK USB need clock indicator. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed.
Page 225: Usb Device Interrupt Enable Register (Usbdevinten - 0X5000 C204)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 193. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description …continued Symbol Description Reset value EP_RLZED Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed.
Page 226: Usb Device Interrupt Set Register
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 196. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit allocation Reset value: 0x0000 0000 Symbol Symbol Symbol ERR_INT EP_RLZED Symbol TxENDPKT CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME ENDPKT Table 197.
Page 227: Usb Device Interrupt Priority Register (Usbdevintpri - 0X5000 C22C)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.10.2.6 USB Device Interrupt Priority register (USBDevIntPri - 0x5000 C22C) Writing one to a bit in this register causes the corresponding interrupt to be routed to the USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the USB_INT_REQ_LP interrupt line.
Page 228: Usb Endpoint Interrupt Enable Register (Usbepinten - 0X5000 C234)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 202. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description Symbol Description Reset value EP0RX Endpoint 0, Data Received Interrupt bit. EP0TX Endpoint 0, Data Transmitted Interrupt bit or sent a NAK.
Page 229: Usb Endpoint Interrupt Clear Register (Usbepintclr - 0X5000 C238)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 203. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit allocation Reset value: 0x0000 0000 Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX Symbol EP11TX EP11RX EP10TX...
Page 230: Usb Endpoint Interrupt Set Register
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 205. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit allocation Reset value: 0x0000 0000 Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX Symbol EP11TX EP11RX EP10TX...
Page 231: Endpoint Realization Registers
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller USBEpIntPri is a write-only register. Table 209. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit allocation Reset value: 0x0000 0000 Symbol EP15TX EP15RX EP14TX E14RX EP13TX EP13RX EP12TX...
Page 232: Usb Realize Endpoint Register
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.10.4.2 USB Realize Endpoint register (USBReEp - 0x5000 C244) Writing one to a bit in this register causes the corresponding endpoint to be realized. Writing zeros causes it to be unrealized. This register returns to its reset state when a bus reset occurs.
Page 233: C248)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller /* Clear the EP_RLZED bit */ Clear EP_RLZED bit in USBDevIntSt; The device will not respond to any transactions to unrealized endpoints. The SIE Configure Device command will only cause realized and enabled endpoints to respond to transactions.
Page 234: Usb Transfer Registers
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.10.5 USB transfer registers The registers in this group are used for transferring data between endpoint buffers and RAM in Slave mode operation. See Section 11.14 “Slave mode operation”. 11.10.5.1 USB Receive Data register (USBRxData - 0x5000 C218) For an OUT transaction, the CPU reads the endpoint buffer data from this register.
Page 235: Usb Transmit Packet Length Register (Usbtxplen - 0X5000 C224)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 217. USB Transmit Data register (USBTxData - address 0x5000 C21C) bit description Symbol Description Reset value 31:0 TX_DATA Transmit Data. 0x0000 0000 11.10.5.4 USB Transmit Packet Length register (USBTxPLen - 0x5000 C224) This register contains the number of bytes transferred from the CPU to the selected endpoint buffer.
Page 236: Sie Command Code Registers
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.10.6 SIE command code registers The SIE command code registers are used for communicating with the Serial Interface Engine. See Section 11.12 “Serial interface engine command description” for more information. 11.10.6.1 USB Command Code register (USBCmdCode - 0x5000 C210) This register is used for sending the command and write data to the SIE.
Page 237: Usb Dma Request Clear Register
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller flag for the DMA engine to start the data transfer if the DMA is enabled for the corresponding endpoint in the USBEpDMASt register. The DMA cannot be enabled for control endpoints (EP0 and EP1). USBDMARSt is a read-only register.
Page 238: Usb Dma Request Set Register
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.10.7.3 USB DMA Request Set register (USBDMARSet - 0x5000 C258) Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register. Writing zero has no effect.
Page 239: Usb Ep Dma Enable Register
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 227. USB EP DMA Status register (USBEpDMASt - address 0x5000 C284) bit description Symbol Value Description Reset value EP0_DMA_ENABLE Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0).
Page 240: Usb Dma Interrupt Enable Register (Usbdmainten - 0X5000 C294)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 230. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description Symbol Value Description Reset value End of Transfer Interrupt bit. All bits in the USBEoTIntSt register are 0.
Page 241: Usb End Of Transfer Interrupt Clear Register (Usbeotintclr - 0X5000 C2A4)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.10.7.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0x5000 C2A4) Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt register. Writing zero has no effect. USBEoTIntClr is a write-only register.
Page 242: Usb System Error Interrupt Status Register (Usbsyserrintst - 0X5000 C2B8)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 237. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0x5000 C2B4) bit description Symbol Value Description Reset value   Set endpoint xx (2  xx  31:0 EPxx 31) new DD interrupt request.
Page 243: Slave Mode
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller The interrupt handling is different for Slave and DMA mode. Slave mode If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For...
Page 244 UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller interrupt event on Slave mode from other Endpoints USBEpIntSt USBDevIntSt FRAME EP_FAST EP_SLOW USBDevIntPri[0] USBEpIntEn[n] USBEpIntPri[n] USBDevIntPri[1] ERR_INT USBDMARSt USBIntSt USB_INT_REQ_HP to NVIC USB_INT_REQ_LP USB_INT_REQ_DMA to DMA engine EN_USB_INTS USBEoTIntST DMA Mode...
Page 245: Serial Interface Engine Command Description
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.12 Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action).
Page 246: Set Address
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 241. SIE command code table Command name Recipient Code (Hex) Data phase Device commands Set Address Device Write 1 byte Configure Device Device Write 1 byte Set Mode Device Write 1 byte...
Page 247: Set Mode (Command: 0Xf3, Data: Write 1 Byte)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 243. Configure Device command bit description Symbol Description Reset value CONF_DEVICE Device is configured. All enabled non-control endpoints will respond. This bit is cleared by hardware when a bus reset occurs. When set, the UP_LED signal is driven LOW if the device is not in the suspended state (SUS=0).
Page 248: Read Test Register (Command: 0Xfd, Data: Read 2 Bytes)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller • In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. • In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device.
Page 249: Get Device Status (Command: 0Xfe, Data: Read 1 Byte)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 245. Set Device Status command bit description Symbol Value Description Reset value Bus Reset bit. On a bus reset, the device will automatically go to the default state. In the default state: •...
Page 250: Read Error Status (Command: 0Xfb, Data: Read 1 Byte)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 246. Get Error Code command bit description Symbol Value Description Reset value Error Code. 0000 No Error. 0001 PID Encoding Error. 0010 Unknown PID. 0011 Unexpected Packet - any packet sequence violation from the specification.
Page 251: Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 248. Select Endpoint command bit description Symbol Value Description Reset value Full/Empty. This bit indicates the full or empty status of the endpoint buffer(s). For IN endpoints, the FE bit gives the ANDed result of the B_1_FULL and B_2_FULL bits.
Page 252: Set Endpoint Status (Command: 0X40 - 0X55, Data: Write 1 Byte (Optional))
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Remark: This command may be invoked by using the USBCmdCode and USBCmdData registers, or by setting the corresponding bit in USBEpIntClr. For ease of use, using the USBEpIntClr register is recommended.
Page 253: Validate Buffer
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller the SETUP data. If it is set then it should discard the previously read data, clear the PO bit by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and again check the status of the PO bit.
Page 254: Slave Mode Operation
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 7. Enable endpoint interrupts (Slave mode): – Clear all endpoint interrupts using USBEpIntClr. – Clear any device interrupts using USBDevIntClr. – Enable Slave mode for the desired endpoints by setting the corresponding bits in USBEpIntEn.
Page 255: Data Transfer For Out Endpoints
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in USBDevIntSt) occurs. 11.14.2 Data transfer for OUT endpoints When the software wants to read the data from an endpoint buffer it should set the RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the USBCtrl register.
Page 256: Transfer Terminology
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.15.1 Transfer terminology Within this section three types of transfers are mentioned: 1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers to these simply as transfers. Within this section they are referred to as USB transfers to distinguish them from DMA transfers.
Page 257: Triggering The Dma Engine
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.15.3 Triggering the DMA engine An endpoint raises a DMA request when Slave mode is disabled by setting the corresponding bit in the USBEpIntEn register to 0 (Section 11.10.3.2) and an endpoint interrupt occurs (see Section 11.10.7.1 “USB DMA Request Status register (USBDMARSt...
Page 258: Next_Dd_Pointer
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Table 251. DMA descriptor Word Access Access Description position (H/W) (S/W) position DMA_mode (00 -Normal; 01 - ATLE) Next_DD_valid (1 - valid; 0 - invalid) Reserved Isochronous_endpoint (1 - isochronous; 0 - non-isochronous)
Page 259: Isochronous_Endpoint
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.15.4.4 Isochronous_endpoint When set, this bit indicates that the descriptor belongs to an isochronous endpoint. Hence 5 words have to be read when fetching it. 11.15.4.5 Max_packet_size The maximum packet size of the endpoint. This parameter is used while transferring the data for IN endpoints from the memory.
Page 260: Packet_Valid
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.15.4.10 Packet_valid This bit is used for isochronous endpoints. It indicates whether the last packet transferred to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was received without errors.
Page 261: Finding Dma Descriptor
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints). 11.15.5.2 Finding DMA Descriptor When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first determine whether a new descriptor has to the fetched or not.
Page 262: No_Packet Dd
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller A DD can have the following types of completion: Normal completion - If the current packet is fully transferred and the Present_DMA_count field equals the DMA_buffer_length, the DD has completed normally. The DD will be written back to memory with DD_retired set and DD_status set to NormalCompletion.
Page 263: Transferring The Data
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.15.6.3 Transferring the Data The data is transferred to or from the memory location DMA_buffer_start_addr. After the end of the packet transfer the Present_DMA_count value is incremented by 1. The isochronous packet size is stored in memory as shown in Figure 31.
Page 264: Auto Length Transfer Extraction (Atle) Mode Operation
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller Next_DD_Pointer NULL DMA_buffer_length Max_packet_size Isochronous_endpoint Next_DD_Valid DMA_mode 0x000A DMA_buffer_start_addr 0x80000000 Present_DMA_Count ATLE settings Packet_Valid DD_Status DD_Retired Isocronous_packetsize_memory_address 0x60000000 after 4 packets 0x000A0010 FULL 0x80000035 frame_ number Packet_Valid Packet_Length EMPTY 0x60000010 data memory packet size memory Fig 31.
Page 265: Out Transfers In Atle Mode
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller OUT transfers in ATLE mode data to be sent data in packets data to be stored in by host driver as seen on USB RAM by DMA engine DMA_buffer_start_addr 160 bytes...
Page 266: In Transfers In Atle Mode
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller In ATLE mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the USB transfer. If the concatenated transfer lengths are such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host will send an empty packet to mark the end of the USB transfer.
Page 267: Ending The Packet Transfer
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11.15.7.4 Ending the packet transfer The DMA engine proceeds with the transfer until the number of bytes specified in the field DMA_buffer_length is transferred to or from on-chip RAM. Then the EOT interrupt will be generated.
Page 268 UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 5. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. Software finds that the active buffer (B_2) has data (FE=1). Software clears the endpoint interrupt and begins reading the contents of B_2.
Page 269: Isochronous Endpoints
UM10360 NXP Semiconductors Chapter 11: LPC176x/5x USB device controller 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. In DMA mode, switching of the active buffer is handled automatically in hardware. For...
Page 270: How To Read This Chapter
UM10360 Chapter 12: LPC176x/5x USB Host controller Rev. 3 — 19 December 2013 User manual 12.1 How to read this chapter The USB host controller is available on the LPC1768, LPC1766, LPC1765, LPC1758, LPC1756, and LPC1754. On these devices, the USB controller can be configured for device, Host, or OTG operation.
Page 271: Features
UM10360 NXP Semiconductors Chapter 12: LPC176x/5x USB Host controller Table 252. USB (OHCI) related acronyms and abbreviations used in this chapter …continued Acronym/abbreviation Description Low Speed OHCI Open Host Controller Interface Universal Serial Bus 12.3.1 Features • OHCI compliant. •...
Page 272: Pin Description
UM10360 NXP Semiconductors Chapter 12: LPC176x/5x USB Host controller 12.4.1 Pin description Table 253. USB Host port pins Pin name Direction Description Type USB_D+ Positive differential data USB Connector USB_D  Negative differential data USB Connector USB_UP_LED GoodLink LED control signal...
Page 273: Usb Host Register Definitions
UM10360 NXP Semiconductors Chapter 12: LPC176x/5x USB Host controller Table 254. USB Host register address definitions …continued Name Address Function Reset value HcControlHeadED 0x5000 C020 Contains the physical address of the first endpoint descriptor of the control list. HcControlCurrentED 0x5000 C024...
Page 274: Chapter 13: Lpc176X/5X Usb Otg
UM10360 Chapter 13: LPC176x/5x USB OTG Rev. 3 — 19 December 2013 User manual 13.1 How to read this chapter The USB OTG controller is available in the LPC1768, LPC1766, LPC1765, LPC1758, LPC1756, and LPC1754. On these devices, the USB controller can be configured for device, Host, or OTG operation.
Page 275: Architecture
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG 13.5 Architecture The architecture of the USB OTG controller is shown below in the block diagram. The host, device, OTG, and I C controllers can be programmed through the register interface. The OTG controller enables dynamic switching between host and device roles through the HNP protocol.
Page 276: Pin Configuration
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG 13.7 Pin configuration The OTG controller has one USB port. Table 255. USB OTG port pins Pin name Direction Description Pin category USB_D+ Positive differential data USB Connector USB_D  Negative differential data...
Page 277: Connecting Usb As A Host
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG 13.7.2 Connecting USB as a host The USB port is connected as host using an embedded USB transceiver. There is no OTG functionality on the port. USB_UP_LED 33 Ω USB_D+ 33 Ω...
Page 278: Register Description
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG 13.8 Register description The OTG and I C registers are summarized in the following table. The Device and Host registers are explained in Table 254 Table 188 in the USB Device Controller and USB Host (OHCI) Controller chapters. All registers are 32 bits wide and aligned to word address boundaries.
Page 279: Otg Interrupt Status Register (Otgintst - 0X5000 C100)
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG Table 257. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description …continued Symbol Description Reset Value USB_HOST_INT USB host interrupt line status. This bit is read-only. USB_ATX_INT External ATX interrupt line status. This bit is read-only.
Page 280: Otg Interrupt Set Register (Otgintset - 0X5000 C20C)
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG 13.8.4 OTG Interrupt Set Register (OTGIntSet - 0x5000 C20C) Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register. Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt.
Page 281: Otg Timer Register (Otgtmr - 0X5000 C114)
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG Table 259. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description …continued Symbol Description Reset Value B_HNP_TRACK Enable HNP tracking for B-device (peripheral), see Section 13.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
Page 282: Otg Clock Status Register (Otgclkst - 0X5000 Cff8)
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG Table 261. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit description …continued Symbol Value Description Reset Value OTG_CLK_EN OTG clock enable Disable the OTG clock. Enable the OTG clock. AHB_CLK_EN AHB master clock enable Disable the AHB clock.
Page 283: C300)
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG Table 263. I C Receive register (I2C_RX - address 0x5000 C300) bit description Symbol Description Reset Value RX Data Receive data. 13.8.11 I C Transmit Register (I2C_TX - 0x5000 C300) This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep.
Page 284 UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG Table 265. I C status register (I2C_STS - address 0x5000 C304) bit description …continued Symbol Value Description Reset Value No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received.
Page 285: C308)
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG Table 265. I C status register (I2C_STS - address 0x5000 C304) bit description …continued Symbol Value Description Reset Value Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.
Page 286: I2C Clock High Register (I2C_Clkhi - 0X5000 C30C)
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG Table 266. I C Control register (I2C_CTL - address 0x5000 C308) bit description …continued Symbol Value Description Reset Value RFDAIE Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e.
Page 287: Hnp Support
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL, to the USB_I2C_INT bit. For more details on the interrupts created by device controller, see the USB device chapter.
Page 288: B-Device: Peripheral To Host Switching
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG The OTG software stack is responsible for implementing the HNP state machines as described in the On-The-Go Supplement to the USB 2.0 Specification. The OTG controller hardware provides support for some of the state transitions in the HNP state machines as described in the following subsections.
Page 289 UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG idle B_HNP_TRACK = 0 B_HNP_TRACK = 1 ? set HNP_FAILURE, clear B_HNP_TRACK, clear PU_REMOVED bus suspended ? disconnect device controller from U1 PU_REMOVED set? set REMOVE_PU PU_REMOVED set? reconnect port U1 to the...
Page 290: Remove D+ Pull-Up
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG b_peripheral when host sends SET_FEATURE with b_hnp_enable, set B_HNP_TRACK REMOVE_PU set? remove D+ pull-up, set PU_REMOVED go to go to b_wait_acon b_peripheral HNP_FAILURE set? add D+ pull-up HNP_SUCCESS set? go to b_host Fig 41.
Page 291: Add D+ Pull-Up
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Add D+ pull-up /* Add D+ pull-up through ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x006;...
Page 292 UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG idle A_HNP_TRACK = 0 A_HNP_TRACK = 1 ? set HNP_FAILURE, clear A_HNP_TRACK disconnect host controller from U1 bus suspended ? resume detected ? connnect host controller back to U1 bus reset detected?
Page 293 UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG a_host when host sends SET_FEATURE with a_hnp_enable, set A_HNP_TRACK set BDIS_ACON_EN in external OTG transceiver load and enable OTG timer suspend host on port 1 go to a_suspend TMR set? HNP_SUCCESS set?
Page 294: Ceiver
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG /* Set BDIS_ACON_EN in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x004; // Send Mode Control 1 (Set) register address OTG_I2C_TX = 0x210; // Set BDIS_ACON_EN bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS &...
Page 295: Load And Enable Otg Timer
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG Load and enable OTG timer /* The following assumes that the OTG timer has previously been */ /* configured for a time scale of 1 ms (TMR_SCALE = “10”) /* and monoshot mode (TMR_MODE = 0)
Page 296: Device Clock Request Signals
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG ahb_slave_clk cclk REGISTER PCUSB INTERFACE ahb_master_clk CLOCK SWITCH AHB_CLK_ON ahb_need_clk AHB_CLK_EN CLOCK dev_dma_need_clk DEVICE USB CLOCK SWITCH CONTROLLER DIVIDER usbclk dev_need_clk DEV_CLK_ON (48 MHz) DEV_CLK_EN CLOCK host_dma_need_clk HOST SWITCH CONTROLLER host_need_clk HOST_CLK_ON...
Page 297: Host Clock Request Signals
UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG The dev_dma_need_clk signal is asserted on any Device controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk.
Page 298 UM10360 NXP Semiconductors Chapter 13: LPC176x/5x USB OTG 5. Follow the appropriate steps in Section 11.13 “USB device controller initialization” initialize the device controller. 6. Follow the guidelines given in the OpenHCI specification for initializing the host controller. UM10360 All information provided in this document is subject to legal disclaimers.
Page 299: Basic Configuration
UM10360 Chapter 14: LPC176x/5x UART0/2/3 Rev. 3 — 19 December 2013 User manual 14.1 Basic configuration The UART0/2/3 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCUART0/2/3. Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled (PCUART2/3 = 0).
Page 300: Pin Description
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 14.3 Pin description Table 269: UARTn Pin description Type Description RXD0, RXD2, RXD3 Input Serial Input. Serial receive data. TXD0, TXD2, TXD3 Output Serial Output. Serial transmit data. 14.4 Register description Each UART contains registers as shown in Table 270.
Page 301 UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 Table 270. UART0/2/3 Register Map Generic Name Description Access Reset UARTn Register value Name & Address RBR (DLAB =0) Receiver Buffer Register. Contains the next received U0RBR - 0x4000 C000 character to be read.
Page 302: Uartn Receiver Buffer Register (U0Rbr - 0X4000 C000, U2Rbr - 0X4009 8000, U3Rbr - 0X4009 C000 When Dlab = 0)
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 14.4.1 UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR - 0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0) The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface.
Page 303: Uartn Interrupt Enable Register (U0Ier - 0X4000 C004, U2Ier - 0X4009 8004, U3Ier - 0X4009 C004 When Dlab = 0)
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 select the right value for UnDLL and UnDLM can be found later in this chapter, see Section 14.4.12. Table 273: UARTn Divisor Latch LSB register (U0DLL - address 0x4000 C000, U2DLL - 0x4009 8000, U3DLL -...
Page 304: Uartn Interrupt Identification Register (U0Iir - 0X4000 C008, U2Iir - 0X4009 8008, U3Iir - 0X4009 C008)
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 14.4.5 UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR - 0x4009 8008, U3IIR - 0x4009 C008) The UnIIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during an UnIIR access, the interrupt is recorded for the next UnIIR access.
Page 305 UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls below the trigger level.
Page 306: Uartn Fifo Control Register (U0Fcr - 0X4000 C008, U2Fcr - 0X4009 8008, U3Fcr - 0X4009 C008)
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 immediately if the UARTn THR FIFO has held two or more characters at one time and currently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs or a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).
Page 307: Uart Transmitter Dma
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 UART transmitter DMA In DMA mode, the transmitter DMA request is asserted on the event of the transmitter FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA controller.
Page 308 UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014) bit description Symbol Value Description Reset Value Receiver Data UnLSR0 is set when the UnRBR holds an unread character and is cleared when Ready (RDR) the UARTn RBR FIFO is empty.
Page 309: Uartn Scratch Pad Register (U0Scr - 0X4000 C01C, U2Scr - 0X4009 801C U3Scr - 0X4009 C01C)
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014) bit description …continued Symbol Value Description Reset Value Error in RX FIFO UnLSR[7] is set when a character with a Rx error such as framing error, parity (RXFE) error or break interrupt, is loaded into the UnRBR.
Page 310: Auto-Baud
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 Table 282: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR - 0x4009 C020) bit description …continued Symbol Value Description Reset value ABEOIntClr End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR.
Page 311: Auto-Baud Modes
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 14.4.10.2 Auto-baud modes When the software is expecting an “AT” command, it configures the UARTn with the expected character format and sets the UnACR Start bit. The initial values in the divisor latches UnDLM and UnDLM don‘t care. Because of the “A” or “a” ASCII coding (”A"...
Page 312: Uartn Irda Control Register (U0Icr - 0X4000 C024, U2Icr - 0X4009 8024, U3Icr - 0X4009 C024)
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' UnACR start rate counter 16xbaud_rate 16 cycles 16 cycles a.
Page 313: Uartn Fractional Divider Register (U0Fdr - 0X4000 C028, U2Fdr - 0X4009 8028, U3Fdr - 0X4009 C028)
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 Table 283: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit description …continued Symbol Value Description Reset value FixPulseEn When 1, enabled IrDA fixed pulse width mode.
Page 314: Baud Rate Calculation
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART0/2/3 disabled making sure that UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this feature.
Page 315 UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
Page 316: Example 2: Pclk = 12 Mhz, Br = 115200
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 Table 286. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778...
Page 317: Architecture
UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 Table 287 describes how to use TXEn bit in order to achieve software flow control. Table 287: UARTn Transmit Enable Register (U0TER - address 0x4000 C030, U2TER - 0x4009 8030, U3TER - 0x4009 C030) bit description...
Page 318 UM10360 NXP Semiconductors Chapter 14: LPC176x/5x UART0/2/3 Transmitter Transmitter Transmitter Un_TXD Transmitter Holding Shift FIFO Register Register Transmitter Interface TX_DMA_REQ TX_DMA_CLR Baud Rate Generator Fractional Main PCLK Rate Divider Divider (DLM, DLL) FIFO Control & Status Interrupt Line Control UARTn interrupt Control &...
Page 319: Chapter 15: Lpc176X/5X Uart1
UM10360 Chapter 15: LPC176x/5x UART1 Rev. 3 — 19 December 2013 User manual 15.1 Basic configuration The UART1 peripheral is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCUART1. Remark: On reset, UART1 is enabled (PCUART1 = 1). 2.
Page 320: Pin Description
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 15.3 Pin description Table 288: UART1 Pin Description Type Description RXD1 Input Serial Input. Serial receive data. TXD1 Output Serial Output. Serial transmit data. CTS1 Input Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via TXD1 from the UART1.
Page 321: Register Description
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 15.4 Register description UART1 contains registers organized as shown in Table 289. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches. Table 289: UART1 register map...
Page 322: Uart1 Receiver Buffer Register (U1Rbr - 0X4001 0000, When Dlab = 0)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 15.4.1 UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0) The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest”...
Page 323: Uart1 Interrupt Enable Register (U1Ier - 0X4001 0004, When Dlab = 0)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Table 292: UART1 Divisor Latch LSB Register (U1DLL - address 0x4001 0000 when DLAB = 1) bit description Symbol Description Reset Value DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the 0x01 baud rate of the UART1.
Page 324: Uart1 Interrupt Identification Register (U1Iir - 0X4001 0008)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description …continued Symbol Value Description Reset Value ABEOIntEn Enables the end of auto-baud interrupt. Disable end of auto-baud Interrupt.
Page 325 UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine.
Page 326: Uart1 Fifo Control Register (U1Fcr - 0X4001 0008)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated when the UART1 THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART1 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up.
Page 327: Uart Receiver Dma
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 UART receiver DMA In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO level becoming equal to or greater than trigger level, or if a character time-out occurs. See the description of the RX Trigger Level above.
Page 328: Auto-Flow Control
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Table 299: UART1 Modem Control Register (U1MCR - address 0x4001 0010) bit description Symbol Value Description Reset value DTR Control Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
Page 329: Auto-Cts
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled, the value of the RTS Control bit is read-only for software.
Page 330: Uart1 Line Status Register (U1Lsr - 0X4001 0014)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 data present in the transmit FIFO and a receiver overrun error can result. Figure 49 illustrates the Auto-CTS functional timing. UART1 TX start bits0..7 stop start bits0..7 stop start bits0..7 stop CTS1 pin Fig 49.
Page 331: Uart1 Modem Status Register (U1Msr - 0X4001 0018)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description …continued Symbol Value Description Reset Value Framing Error When the stop bit of a received character is a logic 0, a framing error occurs. An (FE) U1LSR read clears U1LSR[3].
Page 332: Uart1 Scratch Pad Register (U1Scr - 0X4001 001C)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description Symbol Value Description Reset Value Delta DSR Set upon state change of input DSR. Cleared on an U1MSR read. No change detected on modem input, DSR.
Page 333: Auto-Baud
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description …continued Symbol Value Description Reset value AutoRestart No restart Restart in case of time-out (counter restarts at next UART1 Rx falling edge) Reserved, user software should not write ones to reserved bits.
Page 334: Auto-Baud Modes
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 register is not going to be modified after rate measurement. Also, when auto-baud is used, any write to U1DLM and U1DLL registers should be done before U1ACR register write. The minimum and the maximum baud rates supported by UART1 are function of pclk, number of data bits, stop bits and parity bits.
Page 335: Uart1 Fractional Divider Register (U1Fdr - 0X4001 0028)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a.
Page 336: Baud Rate Calculation
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Table 305: UART1 Fractional Divider Register (U1FDR - address 0x4001 0028) bit description Function Value Description Reset value DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.
Page 337 UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
Page 338: Example 2: Pclk = 12 Mhz, Br = 115200
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Table 306. Fractional Divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778...
Page 339: Uart1 Rs485 Control Register (U1Rs485Ctrl - 0X4001 004C)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Although Table 307 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART1 hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control.
Page 340: Uart1 Rs-485 Address Match Register (U1Rs485Adrmatch - 0X4001 0050)
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description Symbol Value Description Reset value OINV This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 0 The direction control pin will be driven to logic ‘0’...
Page 341: Rs-485/Eia-485 Auto Direction Control
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated.
Page 342: Rs485/Eia-485 Output Inversion
UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 RS485/EIA-485 output inversion The polarity of the direction control signal on the RTS (or DTR) pins can be reversed by programming bit 5 in the U1RS485CTRL register. When this bit is set, the direction control pin will be driven to logic 1 when the transmitter has data waiting to be sent.
Page 343 UM10360 NXP Semiconductors Chapter 15: LPC176x/5x UART1 Transmitter Transmitter Transmitter U1_TXD Transmitter Holding Shift FIFO Register Register Transmitter Interface TX_DMA_REQ TX_DMA_CLR Baud Rate Generator Fractional Main PCLK Rate Divider Divider (DLM, DLL) UART1 interrupt FIFO Control & Status U1_CTS Interrupt...
Page 344: Chapter 16: Lpc176X/5X Can1/2
UM10360 Chapter 16: LPC176x/5x CAN1/2 Rev. 3 — 19 December 2013 User manual 16.1 Basic configuration The CAN1/2 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCAN1/2. Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0). 2.
Page 345: Can Controller Features
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 • Guaranteed latency time for high priority messages. • Programmable transfer rate (up to 1 Mbit/s). • Multicast and broadcast message facility. • Data length from 0 up to 8 bytes. • Powerful error handling capability.
Page 346: Apb Interface Block (Aib)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 • Nested Vectored Interrupt Controller (NVIC) • CAN Transceiver • Common Status Registers INTERFACE CAN CORE APB BUS MANAGEMENT BLOCK LOGIC ERROR MANAGEMENT TRANSCEIVER NVIC LOGIC TRANSMIT BUFFERS 1,2 AND 3 COMMON TIMING...
Page 347: Receive Buffer (Rxb)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 24 23 16 15 Frame info unused TX DLC unused TX Priority Descriptor Field 0 . . . 0 ID.28 ... ID.18 TX Data 4 TX Data 3 TX Data 2 TX Data 1...
Page 348: Error Management Logic (Eml)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 24 23 16 15 10 9 8 7 Frame info unused RX DLC unused ID Index Descriptor Field unused ID.28 ... ID.18 RX Data 4 RX Data 3 RX Data 2 RX Data 1...
Page 349: Global Self Test
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self Reception Request, the transmitted message is also received and stored in the receive buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled.
Page 350: Memory Map Of The Can Block
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.6 Memory map of the CAN block The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows: Table 312. Memory map of the CAN block Address Range Used for 0x4003 8000 - 0x4003 87FF Acceptance Filter RAM.
Page 351 UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 314. CAN1 and CAN2 controller register map …continued Generic Description Access Reset CAN1 & 2 Register Name Name value & Address Bus Timing 0x1C0000 CAN1BTR - 0x4004 4014 CAN2BTR - 0x4004 8014...
Page 352: Can Mode Register (Can1Mod - 0X4004 4000, Can2Mod - 0X4004 8000)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 The internal registers of each CAN Controller appear to the CPU as on-chip memory mapped peripheral registers. Because the CAN Controller can operate in different modes (Operating/Reset, see also Section 16.7.1 “CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD - 0x4004 8000)”), one has to distinguish between different...
Page 353 UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 317. CAN Mode register (CAN1MOD - address 0x4004 4000, CAN2MOD - address 0x4004 8000) bit description Symbol Value Function Reset Value [1][6] Reset Mode. 0 (normal) The CAN Controller is in the Operating Mode, and certain registers can not be written.
Page 354: Can Command Register (Can1Cmr - 0X4004 X004, Can2Cmr - 0X4004 8004)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously. Transmit Priority Mode is explained in more detail in Section 16.5.3 “Transmit Buffers (TXB)”.
Page 355: Can Global Status Register (Can1Gsr - 0X4004 X008, Can2Gsr - 0X4004 8008)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 318. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit description Symbol Value Function Reset Value STB1 Select Tx Buffer 1. 0 (not selected) Tx Buffer 1 is not selected for transmission.
Page 356 UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 319. CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit description Symbol Value Function Reset Value Receive Buffer Status. 0 (empty) No message is available. 1 (full)
Page 357: Rx Error Counter
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.
Page 358: Can Interrupt And Capture Register (Can1Icr - 0X4004 400C, Can2Icr - 0X4004 800C)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 until the Reset Mode is cancelled again. After leaving the Reset Mode, the new TX Counter content is interpreted and the Bus Off event is performed in the same way as if it was forced by a bus error event.
Page 359 UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description …continued Symbol Value Function Reset Value 0 (reset) Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the...
Page 360 UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description …continued Symbol Value Function Reset Value 20:16 ERRBIT Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field.
Page 361: Can Interrupt Enable Register (Can1Ier - 0X4004 4010, Can2Ier - 0X4004 8010)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) bit description …continued Symbol Value Function Reset Value 31:24 ALCBIT Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field.
Page 362: Can Bus Timing Register (Can1Btr -
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 321. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit description …continued Symbol Function Reset Value WUIE Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested.
Page 363: Baud Rate Prescaler
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 322. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit description …continued Symbol Value Function Reset Value Sampling The bus is sampled once (recommended for high speed buses)
Page 364: Can Status Register (Can1Sr - 0X4004 401C, Can2Sr - 0X4004 801C)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Note that a content change of the Error Warning Limit Register is possible only if the Reset Mode was entered previously. An Error Status change (Status Register) and an Error Warning Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again.
Page 365: Can Receive Frame Status Register (Can1Rfs - 0X4004 4020, Can2Rfs - 0X4004 8020)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 324. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description …continued Symbol Value Function Reset Value Transmit Status 2. 0(idle) There is no transmission from Tx Buffer 2.
Page 366: Id Index Field
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 325. CAN Receive Frame Status register (CAN1RFS - address 0x4004 4020, CAN2RFS - address 0x4004 8020) bit description Symbol Function Reset Value ID Index If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier.
Page 367: Can Receive Data Register A (Can1Rda -
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 327. RX Identifier register when FF = 1 Symbol Function Reset Value RM Set 28:0 The 29-bit Identifier field of the current received message. In CAN 2.0B these bits are called ID29-0.
Page 368: Automatic Transmit Priority Detection
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 The values for the reserved bits of the CANxTFI register in the Transmit Buffer should be set to the values expected in the Receive Buffer for an easy comparison, when using the Self Reception facility (self test), otherwise they are not defined.
Page 369: Can Transmit Identifier Register
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Controllers start a Remote Frame transmission with the same identifier simultaneously. For reasons of compatibility no DLC > 8 should be used. If a value greater than 8 is selected, 8 bytes are transmitted in the data frame with the Data Length Code specified in DLC.
Page 370: Can Transmit Data Register B
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 333. CAN Transmit Data register A (CAN1TDA[1/2/3] - address 0x4004 40[38/48/58], CAN2TDA[1/2/3] - address 0x4004 80[38/48/58]) bit description Symbol Function Reset Value RM Set Data 1 If RTR = 0 and DLC ³ 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message.
Page 371: Can Wake-Up Flags Register (Canwakeflags - 0X400F C114)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.7.18 CAN Wake-up Flags register (CANWAKEFLAGS - 0x400F C114) This register provides the wake-up status for the two CAN channels and allows clearing wake-up events. Refer to Section 16.8.2 “Sleep mode” for more information on the CAN sleep feature.
Page 372: Interrupts
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b) software clearing SM in the CAN Mode register.
Page 373: Central Transmit Status Register (Cantxsr - 0X4004 0000)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000) Table 337. Central Transit Status Register (CANTxSR - address 0x4004 0000) bit description Symbol Description Reset Value When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).
Page 374: Central Miscellaneous Status Register (Canmsr - 0X4004 0008)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008) Table 339. Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description Symbol Description Reset Value When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the...
Page 375: Acceptance Filter Off Mode
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.11.1 Acceptance filter Off mode The Acceptance Filter Off Mode is typically used during initialization. During this mode an unconditional access to all registers and to the Look-up Table RAM is possible. With the Acceptance Filter Off Mode, CAN messages are not accepted and therefore not stored in the Receive Buffers of active CAN Controllers.
Page 376: Id Look-Up Table Ram
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.13 ID look-up table RAM The Whole ID Look-up Table RAM is only word accessible. A write access is only possible during the Acceptance Filter Off or Bypass Mode. Read access is allowed in all Acceptance Filter Modes.
Page 377 UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 29 28 CONTROLLER # IDENTIFIER Fig 60. Entry in either extended identifier table The table of ranges of Extended Identifiers must contain an even number of entries, of the same form as in the individual Extended Identifier table. Like the Individual Extended table, the Extended Range must be arranged in ascending numerical order.
Page 378: Acceptance Filter Registers
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.14 Acceptance filter registers 16.14.1 Acceptance Filter Mode Register (AFMR - 0x4003 C000) The AccBP and AccOff bits of the acceptance filter mode register are used for putting the acceptance filter into the Bypass and Off mode. The eFCAN bit of the mode register can be used to activate a FullCAN mode enhancement for received 11-bit CAN ID messages.
Page 379: Standard Frame Individual Start Address Register (Sff_Sa - 0X4003 C004)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.14.3 Standard Frame Individual Start Address register (SFF_sa - 0x4003 C004) Table 343. Standard Frame Individual Start Address register (SFF_sa - address 0x4003 C004) bit description Symbol Description Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 380: Extended Frame Group Start Address Register (Eff_Grp_Sa - 0X4003 C010)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. 16.14.6 Extended Frame Group Start Address register (EFF_GRP_sa - 0x4003 C010) Table 346.
Page 381: Lut Error Address Register (Luterrad - 0X4003 C018)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 information under which address during an ID screening an error in the look-up table was encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up table interrupt. 16.14.9 LUT Error Address register (LUTerrAd - 0x4003 C018) Table 348.
Page 382: Configuration And Search Algorithm
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 352. FullCAN Interrupt and Capture register 1 (FCANIC1 - address 0x4003 C028) bit description Symbol Description Reset Value IntPnd32 FullCan Interrupt Pending bit 32. IntPndx (32<x<63) FullCan Interrupt Pending bit x. IntPnd63 FullCan Interrupt Pending bit 63.
Page 383: Fullcan Mode
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Message Message disable bit disable bit Index 0, 1 SCC = 0 ID = 0x5A FullCAN Explicit Index 2, 3 Standard Frame Index 4, 5 Format Identifier Index 6, 7 Section Explicit Index 8, 9...
Page 384 UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 receive interrupt whenever a CAN message is accepted and received. Software has to move the received message out of the receive buffer from the according CAN controller into the user RAM. To cover dashboard like applications where the controller typically receives data from several CAN channels for further processing, the CAN Gateway block was extended by a so-called FullCAN receive function.
Page 385: Fullcan Message Layout
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.16.1 FullCAN message layout Table 353. Format of automatically stored Rx messages Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 386 UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 START read 1st word SEM == 01? this message has not been SEM == 11? received since last check clear SEM, write back 1 st word read 2nd and 3rd words read 1st word...
Page 387: Fullcan Interrupts
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.16.2 FullCAN interrupts The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM is used for FullCAN objects only.
Page 388: Message Lost Bit And Can Channel Number
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Message Message disable bit disable bit Index 0, 1 11-bit CAN ID 11-bit CAN ID FullCAN Explicit Index 2, 3 11-bit CAN ID 11-bit CAN ID Standard Frame Index 4, 5 11-bit CAN ID...
Page 389: Setting The Interrupt Pending Bits
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.16.2.3 Setting the interrupt pending bits (IntPnd 63 to 0) The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN message and if the interrupt of the according FullCAN Object is enabled (enable bit FCANIntxEn) is set).
Page 390: Scenario 1: Normal Case, No Message Lost . 389 16.16.3.2 Scenario 2: Message Lost
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 semaphore bits IntPndx Write write write write read clear read read read look-up ID, SEM table access MsgLostx message processor handler access access Fig 65. Normal case, no messages lost 16.16.3.2 Scenario 2: Message lost...
Page 391: By Semaphore Bits
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 16.16.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits This scenario is a special case in which the lost message is indicated by the existing semaphore bits. The scenario is entered, if during a Software read of a message object another new message gets stored by the message handler.
Page 392: By Message Lost
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 semaphore bits IntPndx write write clear write write write read clear write write write read read read read read read look-up table access 1st Object 2nd Object write write 2nd Object 1st Object read...
Page 393: Scenario 4: Clearing Message Lost Bit
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 semaphore bits IntPndx look-up write write write write write write read write write write clear read read read write write write table access 1st Object 2nd Object 3rd Object write write write 1st Object...
Page 394: Examples Of Acceptance Filter Tables And Id Index Values
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 semaphore bits IntPndx write write write write write write write write write read clear read read write write write read look-up table access 1st Object 2nd Object 3rd Object write write write 1st Object...
Page 395: Configuration Example 4
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 In cases where explicit identifiers as well as groups of the identifiers are programmed, a CAN identifier search has to start in the explicit identifier section first. If no match is found, it continues the search in the group of identifier section. By this order it can be guaranteed...
Page 396: Configuration Example 6
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 000 d := 000 h := 0 0000 0000 b SFF_sa look-up table RAM ID index # APB base + column_lower column_upper address 00d = 00h 04d = 04h 44d = 2Ch 48d = 30h...
Page 397: Explicit Standard Frame Format Identifier Section (11-Bit Can Id)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Table 356. Used ID-Look-up Table sections ID-Look-up Table Section Status FullCAN not activated Explicit Standard Frame Format activated Group of Standard Frame Format activated Explicit Extended Frame Format activated Group of Extended Frame Format...
Page 398: Configuration Example 7
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 Message Message disable bit disable bit Index SFF_sa ID28 ID28 ID18 ID18 = 0x00 Explicit Standard ID28 ID18 ID28 ID18 Frame Format ID28 ID18 ID28 ID18 Identifier Section Disabled, 7 ID18 ID18 ID28...
Page 399: Fullcan Explicit Standard Frame Format Identifier Section (11-Bit Can Id)
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 FullCAN explicit standard frame format identifier section (11-bit CAN ID) The start address of the FullCAN Explicit Standard Frame Format Identifier section is (automatically) set to 0x00. The end of this section is defined in the SFF_sa register. In the FullCAN ID section only identifiers of FullCAN Object are stored for acceptance filtering.
Page 400: Look-Up Table Programming Guidelines
UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 FullCAN FullCAN Message Message Interrupt Interrupt Disable bit Disable bit Enable bit Enable bit Index FullCAN Disabled, 1 ID28 ID18 ID18 ID28 Explicit Standard ID28 ID18 ID18 ID28 Frame Format ID18 ID18 ID28...
Page 401 UM10360 NXP Semiconductors Chapter 16: LPC176x/5x CAN1/2 • Each section has to be organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) in conjunction with the CAN Identifier (there is no exception for disabled identifiers).
Page 402: Chapter 17: Lpc176X/5X Spi
UM10360 Chapter 17: LPC176x/5x SPI Rev. 3 — 19 December 2013 User manual 17.1 Basic configuration The SPI is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCSPI. Remark: On reset, the SPI is enabled (PCSPI = 1). 2.
Page 403: Pin Description
UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI 17.4 Pin description Table 358. SPI pin description Type Pin Description Name Input/ Serial Clock. The SPI clock signal (SCK) is used to synchronize the transfer of Output data across the SPI interface. The SPI is always driven by the master and received by the slave.
Page 404 UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI SCK (CPOL = 0) SCK (CPOL = 1) SSEL CPHA = 0 Cycle # CPHA = 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8...
Page 405: Spi Peripheral Details
UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI 17.6 SPI peripheral details 17.6.1 General information There are five control and status registers for the SPI port. They are described in detail in Section 17.7 “Register description” on page 407. The SPI Control Register (S0SPCR) contains a number of programmable bits used to control the function of the SPI block.
Page 406: Slave Operation
UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI 3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set after the last cycle of the SPI data transfer. 4. Read the SPI Status Register.
Page 407: Register Description
UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI Register has been read when the SPIF status is active. If the SPI Data Register is written in this time frame, the write data will be lost, and the write collision (WCOL) bit in the SPI Status Register will be activated.
Page 408 UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI Table 361: SPI Control Register (S0SPCR - address 0x4002 0000) bit description Symbol Value Description Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 409: Spi Status Register
UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI 17.7.2 SPI Status Register (S0SPSR - 0x4002 0004) The S0SPSR register controls the operation of SPI0 as per the configuration bits setting shown in Table 362. Table 362: SPI Status Register (S0SPSR - address 0x4002 0004) bit description...
Page 410: Spi Test Control Register
UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI In Master mode, this register must be an even number greater than or equal to 8. Violations of this can result in unpredictable behavior. The SPI0 SCK rate may be calculated as: PCLK_SPI / SPCCR0 value. The SPI peripheral clock is determined by the...
Page 411: Spi Interrupt Register
UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI Table 366: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description Symbol Description Reset Value WCOL Write collision. SPIF SPI transfer complete flag. 31:8 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 412: Architecture
UM10360 NXP Semiconductors Chapter 17: LPC176x/5x SPI 17.8 Architecture The block diagram of the SPI solution implemented in SPI0 interface is shown in the Figure MOSI_IN MOSI_OUT MISO_IN MISO_OUT SPI SHIFT REGISTER SCK_IN SCK_OUT SS_IN SPI CLOCK GENERATOR & DETECTOR...
Page 413: Chapter 18: Lpc176X/5X Ssp0/1
UM10360 Chapter 18: LPC176x/5x SSP0/1 Rev. 3 — 19 December 2013 User manual 18.1 Basic configuration The two SSP interfaces, SSP0 and SSP1 are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCSSP0 to enable SSP0 and bit PCSSP1 to enable SSP1.
Page 414: Pin Descriptions
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 18.4 Pin descriptions Table 368. SSP pin descriptions Interface pin name/function Type Pin Description Name Microwire SCK0/1 Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave. When the SPI interface is used, the clock is programmable to be active-high or active-low, otherwise it is always active-high.
Page 415: Spi Frame Format
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 DX/DR 4 to 16 bits a. Single frame transfer DX/DR 4 to 16 bits 4 to 16 bits b. Continuous/back-to-back frames transfer Fig 76. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two...
Page 416: Spi Format With Cpol=0,Cpha=0
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge.
Page 417: Spi Format With Cpol=0,Cpha=1
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured.
Page 418 UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 SSEL MOSI MISO 4 to 16 bits a. Single transfer with CPOL=1 and CPHA=0 SSEL MOSI MISO 4 to 16 bits 4 to 16 bits b. Continuous transfer with CPOL=1 and CPHA=0 Fig 79. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer) In this configuration, during idle periods: •...
Page 419: Spi Format With Cpol = 1,Cpha = 1
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 18.5.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 80, which covers both single and continuous transfers.
Page 420 UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 8-bit control 4 to 16 bits output data Fig 81. Microwire frame format (single transfer) Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device.
Page 421: Setup And Hold Time Requirements On Cs With Respect To Sk In Microwire Mode
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 8-bit control 4 to 16 bits 4 to 16 bits output data output data Fig 82. Microwire frame format (continuos transfers) 18.5.3.1 Setup and hold time requirements on CS with respect to SK in Microwire...
Page 422: Register Description
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 18.6 Register description The register addresses of the SSP controllers addresses are shown in Table 369. Table 369. SSP Register Map Generic Description Access Reset SSPn Register Name Value Name & Address Control Register 0. Selects the...
Page 423: Sspn Control Register 1 (Ssp0Cr1 -
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 Table 370: SSPn Control Register 0 (SSP0CR0 - address 0x4008 8000, SSP1CR0 - 0x4003 0000) bit description Symbol Value Description Reset Value Data Size Select. This field controls the number of bits 0000 transferred in each frame.
Page 424: Sspn Data Register (Ssp0Dr - 0X4008 8008,
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 Table 371: SSPn Control Register 1 (SSP0CR1 - address 0x4008 8004, SSP1CR1 - 0x4003 0004) bit description Symbol Value Description Reset Value Loop Back Mode. During normal operation. Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).
Page 425: Sspn Status Register (Ssp0Sr - 0X4008 800C, Ssp1Sr - 0X4003 000C)
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 18.6.4 SSPn Status Register (SSP0SR - 0x4008 800C, SSP1SR - 0x4003 000C) This read-only register reflects the current status of the SSP controller. Table 373: SSPn Status Register (SSP0SR - address 0x4008 800C, SSP1SR - 0x4003 000C)
Page 426: Sspn Raw Interrupt Status Register (Ssp0Ris -
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 Table 375: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4008 8014, SSP1IMSC - 0x4003 0014) bit description Symbol Description Reset Value RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received.
Page 427: Sspn Interrupt Clear Register (Ssp0Icr -
UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 Table 377: SSPn Masked Interrupt Status register (SSPnMIS -address 0x4008 801C, SSP1MIS - 0x4003 001C) bit description Symbol Description Reset Value RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
Page 428 UM10360 NXP Semiconductors Chapter 18: LPC176x/5x SSP0/1 Table 379: SSPn DMA Control Register (SSP0DMACR - address 0x4008 8024, SSP1DMACR - 0x4003 0024) bit description Symbol Description Reset Value Receive DMA Enable When this bit is set to one 1, DMA for the receive FIFO is (RXDMAE) enabled, otherwise receive DMA is disabled.
Page 429: Basic Configuration
UM10360 Chapter 19: LPC176x/5x I2C0/1/2 Rev. 3 — 19 December 2013 User manual 19.1 Basic configuration The I C0/1/2 interfaces are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCI2C0/1/2. Remark: On reset, all I C interfaces are enabled (PCI2C0/1/2 = 1).
Page 430: Applications
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 • C0 is a standard I C compliant bus interface with open-drain pins. This interface supports functions described in the I C specification for speeds up to 1 MHz (Fast Mode Plus). This includes multi-master operation and allows powering off this device in a working system while leaving the I C-bus functional.
Page 431: I 2 C Fast Mode Plus
Fast Mode Plus is a 1 Mbit/sec transfer rate to communicate with the I C products which the NXP Semiconductors is now providing. In order to use Fast Mode Plus, the I C0 pins must be configured, then rates above 400...
Page 432: I 2 C Operating Modes
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Any of the I C interfaces brought out to pins other than those just mentioned use standard I/O pins. These pins also support I C operation in fast mode and standard mode. The...
Page 433: Master Receiver Mode
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 SLAVE ADDRESS RW=0 DATA DATA n bytes data transmitted A = Acknowledge (SDA low) from Master to Slave A = Not acknowledge (SDA high) from Slave to Master S = START condition P = STOP condition Fig 85.
Page 434: Slave Receiver Mode
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 After a repeated START condition, I C may switch to the master transmitter mode. DATA DATA DATA n bytes data transmitted A = Acknowledge (SDA low) A = Not acknowledge (SDA high) From master to slave...
Page 435: Slave Transmitter Mode
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.6.4 Slave Transmitter mode The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via SDA while the serial clock is input through SCL.
Page 436: Address Registers, I2Adr0 To I2Adr3
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 ADDRESS REGISTERS I2CnADDR0 to I2CnADDR3 MATCHALL I2CnMMCTRL[3] MASK REGISTERS MASK and COMPARE I2CnMASK0 to I2CnMASK3 INPUT FILTER I2CnDATABUFFER SHIFT REGISTER OUTPUT I2CnDAT STAGE MONITOR MODE REGISTER I2CnMMCTRL BIT COUNTER/ PCLK ARBITRATION and INPUT...
Page 437: Address Mask Registers, I2Mask0 To I2Mask3
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Remark: in the remainder of this chapter, when the phrase “own slave address” is used, it refers to any of the four configured slave addresses after address masking. 19.7.3 Address mask registers, I2MASK0 to I2MASK3 The four mask registers each contain seven active bits (7:1).
Page 438: Serial Clock Generator
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 SDA line SCL line (1) Another device transmits serial data. (2) Another device overrules a logic (dotted line) transmitted this I C master by pulling the SDA line low. Arbitration is lost, and this I C enters Slave Receiver mode.
Page 439: Timing And Control
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 via the I C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above.
Page 440: Register Description
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.8 Register description Each I C interface contains 16 registers as shown in Table 383 below. Remark: In the LPC176x/5x, the following registers have been added to support response to multiple addresses in Slave mode and a new Monitor mode: I2ADR1 to 3, I2MASK0 To 3, MMCTRL, and I2DATA_BUFFER.
Page 441: I C000;2, C000; C000;Ontrol Set Register (Ic000;2,C000;Onset: I C000;2, C000;0, Ic000;2,C000;0C000;Onset - 0X4001 C000;000; I C000;2, C000;1, Ic000;2,C000;1C000;Onset - 0X4005 C000;000; I C000;2, C000;C000;2,, Ic000;2,C000;C000;2,C000;Onset - 0X400A 0000)
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Table 383. I C register map Generic Description Access Reset Cn Name & Address Name value I2ADR2 I2C Slave Address Register 2. Contains the 7-bit 0x00 I2C0ADR2 - 0x4001 C024 slave address for operation of the I...
Page 442 UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Table 384. I C Control Set register (I2CONSET: I C0, I2C0CONSET - address 0x4001 C000, C1, I2C1CONSET - address 0x4005 C000, I C2, I2C2CONSET - address 0x400A 0000) bit description Symbol Description Reset value Reserved.
Page 443: I C018;2, C018; C018;Ontrol C018;Lear Register (Ic018;2,C018;Onc018;Lr: I C018;2, C018;0, Ic018;2,C018;0C018;Onc018;Lr - 0X4001 C018;018; I C018;2, C018;1, Ic018;2,C018;1C018;Onc018;Lr - 0X4005 C018;018; I C018;2, C018;C018;2,, Ic018;2,C018;C018;2,C018;On
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 In slave mode, setting this bit can recover from an error condition. In this case, no STOP condition is transmitted to the bus. The hardware behaves as if a STOP condition has been received and it switches to “not addressed” slave receiver mode. The STO flag is cleared by hardware automatically.
Page 444: I C1,2, C1, Status Register (Ic1,2,Stat: I C1,2, C1,0, Ic1,2,C1,0Stat - 0X4001 C1,004; I C1,2, C1,1, Ic1,2,C1,1Stat - 0X4005 C1,004; I C1,2, C1,C1,2,, Ic1,2,C1,C1,2,Stat - 0X400A 0004)
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Table 385. I C Control Clear register (I2CONCLR: I C0, I2C0CONCLR - 0x4001 C018; C1, I2C1CONCLR - 0x4005 C018; I C2, I2C2CONCLR - 0x400A 0018) bit description …continued Symbol Description Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 445: I2C1Mmctrl- 0X4005 C01C; I 2 C2
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Table 387. I C Data register (I2DAT: I C0, I2C0DAT - 0x4001 C008; I C1, I2C1DAT - 0x4005 C008; I C2, I2C2DAT - 0x400A 0008) bit description Symbol Description Reset value Data This register holds data values that have been received or are to be transmitted.
Page 446: Interrupt In Monitor Mode
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Table 388. I C Monitor mode control register (I2MMCTRL: I C0, I2C0MMCTRL - 0x4001 C01C; C1, I2C1MMCTRL- 0x4005 C01C; I C2, I2C2MMCTRL- 0x400A 001C) bit description …continued Symbol Value Description Reset value MATCH_ALL Select interrupt register match.
Page 447: I2C2Data_Buffer- 0X400A 002C)
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.8.6 I C Data buffer register (I2DATA_BUFFER: I C0, I2CDATA_BUFFER - 0x4001 C02C; I C1, I2C1DATA_BUFFER- 0x4005 C02C; I I2C2DATA_BUFFER- 0x400A 002C) In monitor mode, the I C module may lose the ability to stretch the clock if the ENA_SCL bit is not set.
Page 448: I2C0Mask[0, 1, 2, 3] - 0X4001 C0[30, 34, 38, 3C]; C1, I2C1Mask[0, 1, 2, 3] - Address 0X4005 C0[30, 34, 38, 3C]; I C2, I2C2Mask[0, 1, 2, 3] - Address 0X400A 00[30, 34, 38, 3C])
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.8.8 I C Mask registers (I2MASK0 to 3: I C0, I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C]; I C1, I2C1MASK[0, 1, 2, 3] - address 0x4005 C0[30, 34, 38, 3C]; I...
Page 449: Cycle
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.8.11 Selecting the appropriate I C data rate and duty cycle Software must set values for the registers I2SCLH and I2SCLL to select the appropriate data rate and duty cycle. I2SCLH defines the number of PCLK_I2C cycles for the SCL HIGH time, I2SCLL defines the number of PCLK_I2C cycles for the SCL low time.
Page 450: Details Of I C Operating Modes
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.9 Details of I C operating modes The four operating modes are: • Master Transmitter • Master Receiver • Slave Receiver • Slave Transmitter Data transfers in each mode of operation are shown in...
Page 451: Master Transmitter Mode
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.9.1 Master Transmitter mode In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 93). Before the master transmitter mode can be entered, I2CON must be initialized as follows: Table 396.
Page 452 UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 successful transmission DATA to a Slave Receiver next transfer started with a Repeated Start condition Acknowledge received after the Slave address to Master receive mode, Acknowledge entry received after a = MR Data byte...
Page 453: Master Receiver Mode
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.9.2 Master Receiver mode In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 94). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load I2DAT with the 7-bit slave address and the data direction bit (SLA+R).
Page 454 UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 successful transmission to DATA DATA a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address to Master transmit mode, entry = MT arbitration lost in...
Page 455: Slave Receiver Mode
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.9.3 Slave Receiver mode In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 95). To initiate the slave receiver mode, I2CON register, the I2ADR registers, and the I2MASK registers must be configured.
Page 456 UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 reception of the own Slave address and one DATA DATA P OR S or more Data bytes all are acknowledged last data byte received is Not P OR S acknowledged arbitration lost as...
Page 457: Slave Transmitter Mode
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.9.4 Slave Transmitter mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 96). Data transfer is initialized as in the slave receiver mode. When I2ADR...
Page 458: Detailed State Tables
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.9.5 Detailed state tables The following tables show detailed state information for the four I C operating modes. Table 398. Master Transmitter mode I2CSTAT Status of the Application software response Next action taken by I...
Page 459 UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Table 399. Master Receiver mode I2CSTAT Status of the Application software response Next action taken by I C hardware Status C-bus and To/From I2DAT To I2CON Code hardware STA STO SI 0x08 A START condition Load SLA+R SLA+R will be transmitted;...
Page 460 UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Table 400. Slave Receiver mode I2CSTAT Status of the I C-bus Application software response Next action taken by I C hardware Status and hardware To/From I2DAT To I2CON Code STA STO SI 0x60...
Page 461 UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Table 400. Slave Receiver mode I2CSTAT Status of the I C-bus Application software response Next action taken by I C hardware Status and hardware To/From I2DAT To I2CON Code STA STO SI 0x98...
Page 462 UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 Table 401. Slave Transmitter mode I2CSTAT Status of the I C-bus Application software response Next action taken by I C hardware Status and hardware To/From I2DAT To I2CON Code STA STO SI 0xA8...
Page 463: Miscellaneous States
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.9.6 Miscellaneous states There are two I2STAT codes that do not correspond to a defined I C hardware state (see Table 402). These are discussed below. 19.9.6.1 I2STAT = 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set.
Page 464: Data Transfer After Loss Of Arbitration
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 If the I C hardware detects a repeated START condition on the I C-bus before generating a repeated START condition itself, it will release the bus, and no interrupt request is generated. If another master frees the bus by generating a STOP condition, the I...
Page 465 UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 The I C hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, the I...
Page 466: I 2 C State Service Routines
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.9.8 I C state service routines This section provides examples of operations that must be performed by various I C state service routines. This includes: • Initialization of the I C block after a Reset.
Page 467: Software Example
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.10 Software example 19.10.1 Initialization routine Example to initialize I C Interface as a Slave and/or Master. 1. Load the I2ADR registers and I2MASK registers with values to configure the own Slave Address, enable General Call recognition if needed.
Page 468: Master States
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 19.10.5.2 Master States State 0x08 and State 0x10 are for both Master Transmit and Master Receive modes. The R/W bit decides whether the next state is within Master Transmit mode or Master Receive mode.
Page 469: State: 0X20
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.10.6.2 State: 0x20 Slave Address + Write has been transmitted, NOT ACK has been received. A STOP condition will be transmitted. 1. Write 0x14 to I2CONSET to set the STO and AA bits.
Page 470: State: 0X48
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 3. Exit 19.10.7.2 State: 0x48 Slave Address + Read has been transmitted, NOT ACK has been received. A STOP condition will be transmitted. 1. Write 0x14 to I2CONSET to set the STO and AA bits.
Page 471: State: 0X68
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.10.8.2 State: 0x68 Arbitration has been lost in Slave Address and R/W bit as bus Master. Own Slave Address + Write has been received, ACK has been returned. Data will be received and ACK will be returned.
Page 472: State: 0X88
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.10.8.6 State: 0x88 Previously addressed with own Slave Address. Data has been received and NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit.
Page 473: State: 0Xb0
UM10360 NXP Semiconductors Chapter 19: LPC176x/5x I2C0/1/2 19.10.9.2 State: 0xB0 Arbitration lost in Slave Address and R/W bit as bus Master. Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received.
Page 474: Basic Configuration
UM10360 Chapter 20: LPC176x/5x I2S Rev. 3 — 19 December 2013 User manual 20.1 Basic configuration The I S interface is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCI2S. Remark: On reset, the I S interface is disabled (PCI2S = 0).
Page 475: Description
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S 20.3 Description The I S performs serial data out via the transmit channel and serial data in via the receive channel. These support the NXP Inter IC Audio format for 8-bit, 16-bit and 32-bit audio data, both for stereo and mono modes.
Page 476: Pin Descriptions
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S 20.4 Pin descriptions Table 403. Pin descriptions Pin Name Type Description I2SRX_CLK Input/ Receive Clock. A clock signal used to synchronize the transfer of data on the receive channel. It is Output driven by the master and received by the slave. Corresponds to the signal SCK in the I S-bus specification.
Page 477: Register Description
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S 20.5 Register description Table 404 shows the registers associated with the I S interface and a summary of their functions. Following the table are details for each register. Table 404. I S register map...
Page 478: 0X400A 8004)
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S Table 405: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description …continued Symbol Value Description Reset Value mono When 1, data is of monaural format. When 0, the data is in stereo format.
Page 479: Status Feedback Register (I2Sstate - 0X400A 8010)
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S Table 408: Receive FIFO register (I2RXFIFO - address 0x400A 800C) bit description Symbol Description Reset Value  31:0 I2SRXFIFO 32-bit transmit FIFO. level = 0 20.5.5 Status Feedback register (I2SSTATE - 0x400A 8010) The I2SSTATE register provides status information about the I S interface.
Page 480: Dma Configuration Register 2 (I2Sdma2 - 0X400A 8018)
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S 20.5.7 DMA Configuration Register 2 (I2SDMA2 - 0x400A 8018) The I2SDMA2 register controls the operation of DMA request 2. The function of bits in I2SDMA2 are shown in Table 405. Table 411: DMA Configuration register 2 (I2SDMA2 - address 0x400A 8018) bit description...
Page 481: Notes On Fractional Rate Generators
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be greater than or equal to X. Table 413: Transmit Clock Rate register (I2TXRATE - address 0x400A 8020) bit description...
Page 482: Transmit Clock Bit Rate Register (I2Stxbitrate - 0X400A 8028)
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S Table 414: Receive Clock Rate register (I2SRXRATE - address 0x400A 8024) bit description Symbol Description Reset Value S receive Y_divider MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK.
Page 483: Receive Mode Control Register (I2Srxmode - 0X400A 8034)
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S Table 417: Transmit Mode Control register (I2STXMODE - 0x400A 8030) bit description Symbol Value Description Reset Value TXCLKSEL Clock source selection for the transmit bit clock divider. Select the TX fractional rate divider clock output as the source...
Page 484: S Transmit And Receive Interfaces
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S 20.6 I S transmit and receive interfaces The I S interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio information. Some details of I S implementation are: • When the FIFO is empty, the transmit channel will repeat transmitting the same data until new data is written to the FIFO.
Page 485: S Operating Modes
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S 20.7 I S operating modes The clocking and WS usage of the I S interface is configurable. In addition to master and slave modes, which are independently configurable for the transmitter and the receiver, several different clock sources are possible, including variations that share the clock and/or WS between the transmitter and receiver.
Page 486 UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S I2STXMODE[3] (Pin OE) I2STX_MCLK I2STX_RATE[15:8] I2STX_CLK I2STX_RATE[7:0] I2STXBITRATE[5:0] I2STX_SDA I2S_PCLK 8-bit TX_REF TX bit clock peripheral ÷N ÷2 Fractional block (1 to 64) I2STX_WS Rate Divider (transmit) TX_WS ref Fig 101. Typical transmitter master mode, with or without MCLK output...
Page 487 UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S I2STX_SDA peripheral RX bit clock block I2STX_WS (transmit) RX_WS ref Fig 106. 4-wire transmitter slave mode sharing the receiver bit clock and WS Table 420: I S receive modes I2SDAI I2SRXMODE Description [3:0] 0 0 0 0 Typical receiver master mode.
Page 488 UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S I2SRXMODE[3] (Pin OE) I2SRX_MCLK I2SRX_RATE[15:8] I2SRX_CLK I2SRX_RATE[7:0] I2SRXBITRATE[5:0] I2SRX_SDA I2S_PCLK 8-bit RX_REF RX bit clock peripheral ÷N ÷2 Fractional block (1 to 64) I2SRX_WS Rate Divider (receive) RX_WS ref Fig 107. Typical receiver master mode, with or without MCLK output...
Page 489: Fifo Controller
UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S I2SRX_SDA peripheral TX bit clock block I2SRX_WS (receive) TX_WS ref Fig 112. 4-wire receiver slave mode sharing the transmitter bit clock and WS 20.8 FIFO controller Handling of data for transmission and reception is performed via the FIFO controller which can generate two DMA requests and an interrupt request.
Page 490 UM10360 NXP Semiconductors Chapter 20: LPC176x/5x I2S Mono 8-bit data mode N + 3 N + 2 N + 1 Stereo 8-bit data mode LEFT + 1 RIGHT + 1 LEFT RIGHT Mono 16-bit data mode N + 1 Stereo 16-bit data mode...
Page 491: Chapter 21: Lpc176X/5X Timer 0/1/2/3
UM10360 Chapter 21: LPC176x/5x Timer 0/1/2/3 Rev. 3 — 19 December 2013 User manual 21.1 Basic configuration The Timer 0, 1, 2, and 3 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCTIM0/1/2/3. Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled (PCTIM2/3 = 0).
Page 492: Applications
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 21.3 Applications • Interval Timer for counting internal events. • Pulse Width Demodulator via Capture inputs. • Free running timer. 21.4 Description The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally-supplied clock, and can optionally generate interrupts or perform other actions at specified timer values, based on four match registers.
Page 493: Register Description
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 21.6 Register description Each Timer/Counter contains the registers shown in Table 425 ("Reset Value" refers to the data stored in used bits only; it does not include reserved bits content). More detailed descriptions follow.
Page 494: Interrupt Register (T[0/1/2/3]Ir - 0X4000 4000, 0X4000 8000, 0X4009 0000, 0X4009 4000)
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 Table 425. TIMER/COUNTER0-3 register map …continued Generic Description Access Reset TIMERn Register/ Name Value Name & Address Capture Register 0. CR0 is loaded with the value of TC when there T0CR0 - 0x4000 402C is an event on the CAPn.0(CAP0.0 or CAP1.0 respectively) input.
Page 495: Count Control Register (T[0/1/2/3]Ctcr - 0X4000 4070, 0X4000 8070, 0X4009 0070, 0X4009 4070)
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 Table 427. Timer Control Register (TCR, TIMERn: TnTCR - addresses 0x4000 4004, 0x4000 8004, 0x4009 0004, 0x4009 4004) bit description Symbol Description Reset Value Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
Page 496: Timer Counter
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 Table 428. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070, 0x4009 4070) bit description …continued Symbol Value Description Reset Value Count When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for Input clocking.
Page 497: Match Registers (Mr0 - Mr3)
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 21.6.7 Match Registers (MR0 - MR3) The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer.
Page 498: Capture Registers (Cr0 - Cr1)
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 21.6.9 Capture Registers (CR0 - CR1) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture...
Page 499: Dma Operation
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 Match events for Match 0 and Match 1 in each timer can cause a DMA request, see Section 21.6.12. Table 431. External Match Register (T[0/1/2/3]EMR - addresses 0x4000 403C, 0x4000 803C, 0x4009 003C,...
Page 500: Example Timer Operation
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 the GPDMA controller. Remark: Because timer DMA requests are generated whenever the timer value is equal to the related Match Register value, DMA requests are always generated when the timer is running, unless the Match Register value is higher than the upper count limit of the timer.
Page 501: Architecture
UM10360 NXP Semiconductors Chapter 21: LPC176x/5x Timer 0/1/2/3 21.8 Architecture The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in Figure 116. MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER...
Page 502: Features
UM10360 Chapter 22: LPC176x/5x Repetitive Interrupt Timer (RIT) Rev. 3 — 19 December 2013 User manual 22.1 Features • 32-bit counter running from PCLK. Counter can be free-running, or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask.
Page 503: Ri Control Register (Rictrl - 0X400B 0008)
UM10360 NXP Semiconductors Chapter 22: LPC176x/5x Repetitive Interrupt Timer (RIT) 22.3.3 RI Control register (RICTRL - 0x400B 0008) Table 436. RI Control register (RICTRL - address 0x400B 0008) bit description Symbol Value Description Reset value RITINT Interrupt flag This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers.
Page 504 UM10360 NXP Semiconductors Chapter 22: LPC176x/5x Repetitive Interrupt Timer (RIT) Counting can be halted in software by writing a ‘0’ to the Enable_Timer bit - RICTRL(3). Counting will also be halted when the processor is halted for debugging provided the Enable_Break bit –...
Page 505: Basic Configuration
UM10360 Chapter 23: LPC176x/5x System Tick Timer Rev. 3 — 19 December 2013 User manual 23.1 Basic configuration The System Tick Timer is configured using the following registers: 1. Clock Source: Select either the internal CCLK or external STCLK (P3.26) clock as the source in the STCTRL register.
Page 506: Register Description
UM10360 NXP Semiconductors Chapter 23: LPC176x/5x System Tick Timer STCALIB STRELOAD load data STCURR private cclk peripheral 24-bit down counter clock STCLK pin under- count flow enable load ENABLE CLKSOURCE STCTRL COUNTFLAG TICKINT System Tick interrupt Fig 118. System Tick Timer block diagram 23.5 Register description...
Page 507: System Timer Reload Value Register (Streload - 0Xe000 E014)
UM10360 NXP Semiconductors Chapter 23: LPC176x/5x System Tick Timer Table 439. System Timer Control and status register (STCTRL - 0xE000 E010) bit description …continued Symbol Description Reset value 15:3 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
Page 508 UM10360 NXP Semiconductors Chapter 23: LPC176x/5x System Tick Timer Table 442. System Timer Calibration value register (STCALIB - 0xE000 E01C) bit description Symbol Value Description Reset value 23:0 TENMS Reload value to get a 10 millisecond System Tick underflow rate when running 0x0F 423F at 100 MHz.
Page 509: Example Timer Calculations
UM10360 NXP Semiconductors Chapter 23: LPC176x/5x System Tick Timer 23.6 Example timer calculations The following examples illustrate selecting System Tick Timer values for different system configurations. All of the examples calculate an interrupt interval of 10 milliseconds, as the System Tick Timer is intended to be used.
Page 510: Chapter 24: Lpc176X/5X Pulse Width Modulator (Pwm)
UM10360 Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) Rev. 3 — 19 December 2013 User manual 24.1 Basic configuration The PWM is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCPWM1. Remark: On reset, the PWM is enabled (PCPWM1 = 1). 2.
Page 511: Description
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) 24.3 Description The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC176x/5x. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers.
Page 512 UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) MATCH SHADOW REGISTER 0 REGISTER 0 LOAD ENABLE MATCH SHADOW REGISTER 1 REGISTER 1 LOAD ENABLE MATCH SHADOW REGISTER 2 REGISTER 2 LOAD ENABLE MATCH SHADOW REGISTER 3 REGISTER 3...
Page 513: Sample Waveform With Rules For Single And Double Edge Control
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) 24.4 Sample waveform with rules for single and double edge control A sample of how PWM values relate to waveform outputs is shown in Figure 120. PWM output logic is shown in...
Page 514: Rules For Single Edge Controlled Pwm Outputs
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) 24.4.1 Rules for Single Edge Controlled PWM Outputs 1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0.
Page 515: Register Description
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input can not exceed one quarter of the PCLK clock.
Page 516: Pwm Interrupt Register (Pwm1Ir - 0X4001 8000)
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) Table 445. PWM1 register map …continued Generic Description Access Reset PWMn Register Name Value Name & Address Capture Register 2. See CR0 description. PWM1CR2 - 0x4001 8034 Capture Register 3. See CR0 description.
Page 517: Pwm Timer Control Register (Pwm1Tcr 0X4001 8004)
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) Table 446: PWM Interrupt Register (PWM1IR - address 0x4001 8000) bit description …continued Symbol Description Reset Value PWMMR5 Interrupt Interrupt flag for PWM match channel 5. PWMMR6 Interrupt Interrupt flag for PWM match channel 6.
Page 518: Pwm Match Control Register (Pwm1Mcr - 0X4001 8014)
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) Table 448. PWM Count control Register (PWM1CTCR - address 0x4001 8070) bit description Symbol Value Description Reset Value Counter/ Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Timer Mode Register.
Page 519: Pwm Capture Control Register (Pwm1Ccr - 0X4001 8028)
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description …continued Symbol Value Description Reset Value PWMMR2S Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be set to 0 if PWMMR2 matches the PWMTC.
Page 520: Pwm Control Register (Pwm1Pcr - 0X4001 804C)
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for that input in this register should be programmed as 000, but capture and/or interrupt can be selected for the other 3 CAP inputs.
Page 521: Pwm Latch Enable Register (Pwm1Ler - 0X4001 8050)
UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) Table 451: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description …continued Symbol Value Description Reset Value PWMENA1 The PWM1 output enabled. The PWM1 output disabled. PWMENA2 The PWM2 output enabled.
Page 522 UM10360 NXP Semiconductors Chapter 24: LPC176x/5x Pulse Width Modulator (PWM) Table 452: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description Symbol Description Reset Value Enable PWM Writing a one to this bit allows the last value written to the PWM Match 0 register to be Match 0 Latch become effective when the timer is next reset by a PWM Match event.
Page 523: Chapter 25: Lpc176X/5X Motor Control Pwm
UM10360 Chapter 25: LPC176x/5x Motor control PWM Rev. 3 — 19 December 2013 User manual 25.1 Introduction The Motor Control PWM (MCPWM) is optimized for three-phase AC and DC motor control applications, but can be used in many other applications that need timing, counting, capture, and comparison.
Page 524: Block Diagram
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.4 Block Diagram PCLK MCI0-2 Clock Event Clock Event Clock Event selection selection selection selection selection selection MCCNTCON MCCAPCON cntl cntl cntl MAT0 MAT1 MAT2 ACMODE ACMODE (write) (write) (write) MAT0...
Page 525: Configuring Other Modules For Mcpwm Use
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.5 Configuring other modules for MCPWM use Configure the following registers in other modules before using the Motor Control PWM: 1. Power: in the PCONP register (Table 46), set bit PCMCPWM.
Page 526: Register Description
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.7 Register description “Control” registers and “interrupt” registers have separate read, set, and clear addresses. Reading such a register’s read address(e.g. MCCON) yields the state of the register bits. Writing ones to the set address (e.g. MCCON_SET) sets register bit(s), and writing ones to the clear address (e.g.
Page 527: Mcpwm Control Register
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.7.1 MCPWM Control register 25.7.1.1 MCPWM Control read address (MCCON - 0x400B 8000) The MCCON register controls the operation of all channels of the PWM. This address is read-only, but the underlying register can be modified by writing to addresses MCCON_SET and MCCON_CLR.
Page 528: Mcpwm Control Set Address
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM Table 455. MCPWM Control read address (MCCON - 0x400B 8000) bit description …continued Symbol Value Description Reset value 15:13 Reserved. RUN2 Stops/starts timer channel 2. Stop. Run. CENTER2 Edge/center aligned operation for channel 2.
Page 529: 0X400B 8008)
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.7.1.3 MCPWM Control clear address (MCCON_CLR - 0x400B 8008) Writing ones to this write-only address clears the corresponding bits in MCCON. Table 457. MCPWM Control clear address (MCCON_CLR - 0x400B 8008) bit description...
Page 530: Mcpwm Capture Control Set Address (Mccapcon_Set - 0X400B 8010)
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.7.2.2 MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) Writing ones to this write-only address sets the corresponding bits in MCCAPCON. Table 459. MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) bit description...
Page 531: Mcpwm Interrupt Enable Set Address
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.7.3.2 MCPWM Interrupt Enable set address (MCINTEN_SET - 0x400B 8054) Writing ones to this write-only address sets the corresponding bits in MCINTEN, thus enabling interrupts. Table 464. PWM interrupt enable set register (MCINTEN_SET - address 0x400B 8054) bit...
Page 532: Mcpwm Count Control Register
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM Table 468. MCPWM Interrupt Flags clear address (PWMINTF_CLR - 0x400B 8070) bit description Description 31:0 Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF register, thus clearing the corresponding interrupt request(s). See Table 462.
Page 533: Mcpwm Count Control Set Address (Mccntcon_Set - 0X400B 8060)
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM Table 469. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description …continued Symbol Value Description Reset Value TC2MCI0_FE If MODE2 is 1, counter 2 advances on a falling edge on MCI0.
Page 534: Mcpwm Limit 0-2 Registers
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM Table 472. MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018, 0x400B 801C, 0x400B 8020) bit description Symbol Description Reset value 31:0 MCTC0/1/2 Timer/Counter values for channels 0, 1, 2. 25.7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028, 0x400B 802C) These registers hold the limiting values for timer/counters 0-2.
Page 535: Mcpwm Match 0-2 Registers
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.7.7 MCPWM Match 0-2 registers (MCMAT0-2 - 0x400B 8030, 0x400B 8034, 0x400B 8038) These registers also have “write” and “operating” versions as described above for the Limit registers, and the operating registers are also compared to the channels’ TCs. See 25.7.6...
Page 536: Mcpwm Dead-Time Register (Mcdt - 0X400B 803C)
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.7.8 MCPWM Dead-time register (MCDT - 0x400B 803C) This register holds the dead-time values for the three channels. If a channel’s DTE bit in MCCON is 1 to enable its dead-time counter, the counter counts down from this value whenever one its channel’s outputs changes from “active”...
Page 537: Mcpwm Capture Registers
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.7.10 MCPWM Capture Registers 25.7.10.1 MCPWM Capture read addresses (MCCAP0-2 - 0x400B 8044, 0x400B 8048, 0x400B 804C) The MCCAPCON register (Table 458) allows software to select any edge(s) on any of the MCI0-2 inputs as a capture event for each channel.
Page 538: Pwm Operation
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM 25.8 PWM operation 25.8.1 Pulse-width modulation Each channel of the MCPWM has two outputs, A and B, that can drive a pair of transistors to switch a controlled point between two power rails. Most of the time the two outputs have opposite polarity, but a dead-time feature can be enabled (on a per-channel basis) to delay both signals’...
Page 539: Dead-Time Counter
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM active active passive passive MCOB passive active passive active MCOA POLA = 0 Fig 123. Center-aligned PWM waveform without dead time, POLA = 0 Dead-time counter When the a channel’s DTE bit is set in MCCON, the dead-time counter delays the passive-to-active transitions of both MCO outputs.
Page 540: Shadow Registers And Simultaneous Updates 540 Fast Abort (Abort)
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM active active passive passive MCOB active active passive passive POLA = 0 MCOA Fig 125. Center-aligned waveform with dead time, POLA = 0 25.8.2 Shadow registers and simultaneous updates The Limit, Match, and Commutation Pattern registers (MCLIM, MCMAT, and MCCP) are implemented as register pairs, each consisting of a write register and an operational register.
Page 541: External Event Counting (Counter Mode)
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM If a channel’s HNF bit in the MCCAPCON register is set to enable “noise filtering”, a selected edge on an MCI pin starts the dead-time counter for that channel, and the capture event actions described below are delayed until the dead-time counter reaches 0.
Page 542: Three Phase Ac Mode
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM MCOB2 CCPB2 = 1, on-state CCPA2 = 1, on-state MCOA2 MCOB1 CCPB1 = 0, off-state MCOA1 CCPA1 = 1, on-state MCOB0 CCPB0 = 0, off-state CCPA0 = 1, on-state MCOA0 POLA0 = 0, INVBDC = 0 Fig 126.
Page 543: Interrupts
UM10360 NXP Semiconductors Chapter 25: LPC176x/5x Motor control PWM MCOB2 POLA2 = 0 MCOA2 MAT2 MAT2 MCOB1 POLA1 = 0 MCOA1 MAT1 MAT1 MCOB0 POLA0 = 0 MCOA0 MAT0 LIM0 LIM0 timer reset timer reset Fig 127. Three-phase AC mode sample waveforms, edge aligned PWM mode 25.8.8 Interrupts...
Page 544: Chapter 26: Lpc176X/5X Quadrature Encoder Interface (Qei)
UM10360 Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) Rev. 3 — 19 December 2013 User manual 26.1 Basic configuration The QEI is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCQEI. Remark: On reset, the QEI is disabled (PCQEI = 0). 2.
Page 545 UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) VELOCITY velocity interrupt TIMER (TIM_Int) VELOCITY RELOAD low velocity interrupt VELOCITY (LVEL_Int) COMPARE VELOCITY CAPTURE index Ph A VELOCITY DIGITAL QUAD FILTER COUNTER Ph B DECODER PCLK encoder clock interrupt...
Page 546: Functional Description
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) 26.4 Functional description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel.
Page 547: Digital Input Filtering
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) Table 481. Encoder direction DIR bit DIRINV bit direction forward reverse reverse forward Figure 129 shows how quadrature encoder signals equate to direction and count. direction position -1 -1 -1 -1...
Page 548: Velocity Compare
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) number of edges counted in a given time period is directly proportional to the velocity of the encoder. Setting the reset velocity bit (RESV) has the same effect as an overflow of the velocity timer, except that the setting the RESV bit will not generate a velocity interrupt.
Page 549: Pin Description
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) 26.5 Pin description Table 482. QEI pin description Pin name Description MCI0 Used as the Phase A (PhA) input to the Quadrature Encoder Interface. MCI1 Used as the Phase B (PhB) input to the Quadrature Encoder Interface.
Page 550: Register Description
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) 26.6 Register description 26.6.1 Register summary Table 483. QEI Register summary Name Description Access Reset Address value Control registers QEICON Control register 0x400B C000 QEICONF Configuration register 0x400B C008 QEISTAT...
Page 551: Control Registers
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) 26.6.2 Control registers 26.6.2.1 QEI Control register (QEICON - 0x400B C000) This register contains bits which control the operation of the position and velocity counters of the QEI module. Table 484: QEI Control register (QEICON - address 0x400B C000) bit description...
Page 552: Position, Index And Timer Registers
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) 26.6.3 Position, index and timer registers 26.6.3.1 QEI Position register (QEIPOS - 0x400B C00C) This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation.
Page 553: Qei Position Compare Register 2 (Cmpos2 - 0X400B C01C)
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) 26.6.3.5 QEI Position Compare register 2 (CMPOS2 - 0x400B C01C) This register contains a position compare value. This value is compared against the current value of the position register. Interrupts can be enabled to interrupt when the compare value is equal to the current value of the position register.
Page 554: C030)
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) Table 495: QEI Timer register (QEITIME - address 0x400B C02C) bit description Symbol Description Reset value 31:0 Current velocity timer value. 26.6.3.10 QEI Velocity register (QEIVEL - 0x400B C030) This register contains the running count of velocity pulses for the current time period.
Page 555: Interrupt Registers
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) 26.6.4 Interrupt registers 26.6.4.1 QEI Interrupt Status register (QEIINTSTAT) This register provides the status of the encoder interface and the current set of interrupt sources that are asserted to the controller. Bits set to 1 indicate the latched events that have occurred;...
Page 556: Qei Interrupt Clear Register (Qeiclr - 0X400B Cfe8)
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) Table 501: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description …continued Symbol Description Reset value POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.
Page 557: Qei Interrupt Enable Set Register (Qeiies - 0X400B Cfdc)
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) Table 503: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description …continued Symbol Description Reset value ERR_Int Indicates that an encoder phase error was detected. ENCLK_Int Indicates that and encoder clock pulse was detected.
Page 558: Qei Interrupt Enable Clear Register (Qeiiec - 0X400B Cfd8)
UM10360 NXP Semiconductors Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI) 26.6.4.6 QEI Interrupt Enable Clear register (QEIIEC - 0x400B CFD8) Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable register (QEIIE).
Page 559: Basic Configuration
UM10360 Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers Rev. 3 — 19 December 2013 User manual 27.1 Basic configuration The RTC is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bits PCRTC. Remark: On reset, the RTC is enabled.
Page 560: Architecture
UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers 27.4 Architecture to main regulator DD(REG)(3v3) RTC power domain Ultra-low Power Backup power selector Registers regulator RTC power RTCX1 Ultra-low 1 Hz clock Real Time Clock RTC Alarm...
Page 561: Pin Description
UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers 27.5 Pin description Table 506. RTC pin description Name Type Description RTCX1 Input to the RTC oscillator circuit. RTCX2 Output from the RTC oscillator circuit. Remark: If the RTC is not used, the RTCX1/2 pins can be left floating.
Page 562 UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers Table 507. Real-Time Clock register map Name Description Access Reset Address Value Miscellaneous registers (see Section 27.6.2) Interrupt Location Register 0x4002 4000 Clock Control Register 0x4002 4008 CIIR...
Page 563: Rtc Interrupts
UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers 27.6.1 RTC interrupts Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register (AMR). Interrupts are generated only by the transition into the interrupt state. The ILR separately enables CIIR and AMR interrupts.
Page 564: Counter Increment Interrupt Register (Ciir - 0X4002 400C)
UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers Table 509. Clock Control Register (CCR - address 0x4002 4008) bit description …continued Symbol Value Description Reset value CTCRST CTC Reset. When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero.
Page 565: 0X4002 405C)
UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers Table 511. Alarm Mask Register (AMR - address 0x4002 4010) bit description Symbol Description Reset value AMRSEC When 1, the Second value is not compared for the alarm.
Page 566: Consolidated Time Registers
UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers 27.6.3 Consolidated time registers The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. The...
Page 567: Time Counter Group
UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers Table 516. Consolidated Time register 2 (CTIME2 - address 0x4002 401C) bit description Symbol Description Reset value 11:0 Day of Year Day of year value in the range of 1 to 365 (366 for leap years).
Page 568: Calibration Procedure
UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers Table 519. Calibration register (CALIBRATION - address 0x4002 4040) bit description Symbol Value Description Reset value 16:0 CALVAL If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours.
Page 569: General Purpose Registers
UM10360 NXP Semiconductors Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers 27.6.6 General purpose registers 27.6.6.1 General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses 0x4002 4044 to 0x4002 4054) These registers can be used to store important information when the main power supply is off.
Page 570: Chapter 28: Lpc176X/5X Watchdog Timer (Wdt)
UM10360 Chapter 28: LPC176x/5x Watchdog Timer (WDT) Rev. 3 — 19 December 2013 User manual 28.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled.
Page 571: Description
UM10360 NXP Semiconductors Chapter 28: LPC176x/5x Watchdog Timer (WDT) 28.3 Description The Watchdog consists of a divide by 4 fixed pre-scaler and a 32-bit counter. The clock is fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value from which the counter decrements is 0xFF.
Page 572: Watchdog Mode Register (Wdmod - 0X4000 0000)
UM10360 NXP Semiconductors Chapter 28: LPC176x/5x Watchdog Timer (WDT) 28.4.1 Watchdog Mode register (WDMOD - 0x4000 0000) The WDMOD register controls the operation of the Watchdog as per the combination of WDEN and RESET bits. Note that a watchdog feed must be performed before any changes to the WDMOD register take effect.
Page 573: Watchdog Timer Constant Register (Wdtc - 0X4000 0004)
UM10360 NXP Semiconductors Chapter 28: LPC176x/5x Watchdog Timer (WDT) 28.4.2 Watchdog Timer Constant register (WDTC - 0x4000 0004) The WDTC register determines the time-out value. Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB set to 1 on reset.
Page 574: Block Diagram
UM10360 NXP Semiconductors Chapter 28: LPC176x/5x Watchdog Timer (WDT) Table 528: Watchdog Timer Clock Source Selection register (WDCLKSEL, address 0x4000 0010) bit description Symbol Value Description Reset Value WDSEL These bits select the clock source for the Watchdog timer as described below.
Page 575: Basic Configuration
UM10360 Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC) Rev. 3 — 19 December 2013 User manual 29.1 Basic configuration The ADC is configured using the following registers: 1. Power: In the PCONP register (Table 46), set the PCADC bit. Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit, and then enable the ADC in the AD0CR register (bit PDN Table 531).
Page 576: Pin Description
UM10360 NXP Semiconductors Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC) 29.4 Pin description Table 529 gives a brief summary of each of ADC related pins. Table 529. ADC pin description Type Description AD0.7 to AD0.0 Input Analog Inputs. The ADC cell can measure the voltage on any of these input signals.
Page 577: Register Description
UM10360 NXP Semiconductors Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC) 29.5 Register description The A/D Converter registers are shown in Table 530. Table 530. ADC registers Generic Description Access Reset AD0 Name & Name value Address ADCR A/D Control Register. The ADCR register must be written to select the AD0CR - operating mode before A/D conversion can occur.
Page 578: A/D Control Register (Ad0Cr - 0X4003 4000)
UM10360 NXP Semiconductors Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC) 29.5.1 A/D Control Register (AD0CR - 0x4003 4000) Table 531: A/D Control Register (AD0CR - address 0x4003 4000) bit description Symbol Value Description Reset value Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0 0x01 selects Pin AD0.0, and bit 7 selects pin AD0.7.
Page 579: A/D Global Data Register (Ad0Gdr - 0X4003 4004)
UM10360 NXP Semiconductors Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC) 29.5.2 A/D Global Data Register (AD0GDR - 0x4003 4004) The A/D Global Data Register holds the result of the most recent A/D conversion that has completed, and also includes copies of the status flags that go with that conversion.
Page 580: A/D Data Registers (Ad0Dr0 To Ad0Dr7 - 0X4003 4010 To 0X4003 402C)
UM10360 NXP Semiconductors Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC) Table 533: A/D Interrupt Enable register (AD0INTEN - address 0x4003 400C) bit description …continued Symbol Value Description Reset value ADINTEN3 Completion of a conversion on ADC channel 3 will not generate an interrupt.
Page 581: A/D Status Register (Adstat - 0X4003 4030)
UM10360 NXP Semiconductors Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC) 29.5.5 A/D Status register (ADSTAT - 0x4003 4030) The A/D Status register allows checking the status of all A/D channels simultaneously. The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel are mirrored in ADSTAT.
Page 582: Operation
UM10360 NXP Semiconductors Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC) 29.6 Operation Once an ADC conversion is started, it cannot be interrupted. A new software write to launch a new conversion or a new edge-trigger event will be ignored while the previous conversion is in progress.
Page 583: Basic Configuration
UM10360 Chapter 30: LPC176x/5x Digital-to-Analog Converter (DAC) Rev. 3 — 19 December 2013 User manual 30.1 Basic configuration The DAC is configured using the following registers: 1. Power: The DAC is always connected to V . Register access is determined by PINSEL and PINMODE settings (see below).
Page 584: Register Description
UM10360 NXP Semiconductors Chapter 30: LPC176x/5x Digital-to-Analog Converter (DAC) 30.4 Register description The DAC registers are shown in Table 538. Note that the DAC does not have a control bit in the PCONP register. To enable the DAC, its output must be selected to appear on the related pin, P0.26, by configuring the PINSEL1 register.
Page 585: D/A Converter Counter Value Register
UM10360 NXP Semiconductors Chapter 30: LPC176x/5x Digital-to-Analog Converter (DAC) Table 540. D/A Control register (DACCTRL - address 0x4008 C004) bit description Symbol Value Description Reset Value INT_DMA_REQ 0 This bit is cleared on any write to the DACR register. This bit is set by hardware when the timer times out.
Page 586 UM10360 NXP Semiconductors Chapter 30: LPC176x/5x Digital-to-Analog Converter (DAC) If either the CNT_ENA or the DBLBUF_ENA bits are 0, any writes to the DACR address will go directly to the DACR register. pbus CNTVAL pbus pbus_wr_toDACR pbus PRE-BUFFER DMA_ena COUNTER...
Page 587: Basic Configuration
UM10360 Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Rev. 3 — 19 December 2013 User manual 31.1 Basic configuration The GPDMA is configured using the following registers: 1. Power: In the PCONP register (Table 46), set bit PCGPDMA. Remark: On reset, the GPDMA is disabled (PCGPDMA = 0). 2.
Page 588: Functional Description
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred.
Page 589: Control Logic And Register Bank
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.4.1.2 Control logic and register bank The register block stores data written or to be read across the AHB interface. 31.4.1.3 DMA request and response interface Section 31.4.2 for information on the DMA request and response interface.
Page 590 UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 542. Endian behavior Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane Little Little 1/[7:0] 1/[7:0] 21212121 2/[15:8]...
Page 591: Error Conditions
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 542. Endian behavior …continued Source Destination Source Destination Source Source data Destination Destination data endian endian width width transfer transfer no/byte lane no/byte lane 1/[31:24] 1/[15:0] 12341234 2/[23:16] 2/[31:16]...
Page 592: Channel Hardware
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.4.1.7 Channel hardware Each stream is supported by a dedicated hardware channel, including source and destination controllers, as well as a FIFO. This enables better latency than a DMA controller with only a single hardware channel shared between several DMA streams and simplifies the control logic.
Page 593: Dma Request Connections
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) DMACTC[15:0] — DMA terminal count signals. The DMACTC signal can be used by the DMA controller to indicate to the peripheral that the DMA transfer is complete. 31.4.2.3 DMA request connections The connection of the GPDMA to the supported peripheral devices depends on the DMA functions implemented in those peripherals.
Page 594: Register Description
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.5 Register description The DMA Controller supports 8 channels. Each channel has registers specific to the operation of that channel. Other registers controls aspects of how source peripherals relate to the DMA Controller. There are also global DMA control and status registers.
Page 595 UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 544. GPDMA register map Name Description Access Reset Address state DMACC2Config DMA Channel 2 Configuration Register 0x5000 4150 Channel 3 registers DMACC3SrcAddr DMA Channel 3 Source Address Register 0x5000 4160...
Page 596: Dma Interrupt Status Register (Dmacintstat - 0X5000 4000)
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.5.1 DMA Interrupt Status register (DMACIntStat - 0x5000 4000) The DMACIntStat Register is read-only and shows the status of the interrupts after masking. A 1 bit indicates that a specific DMA channel interrupt request is active. The request can be generated from either the error or terminal count interrupt requests.
Page 597: Dma Interrupt Error Clear Register (Dmacinterrclr - 0X5000 4010)
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 548. DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C) Name Function IntErrStat Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request.
Page 598: Dma Enabled Channel Register (Dmacenbldchns - 0X5000 401C)
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 551. DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018) Name Function RawIntErrStat Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request.
Page 599: Dma Software Single Request Register (Dmacsoftsreq - 0X5000 4024)
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.5.10 DMA Software Single Request register (DMACSoftSReq - 0x5000 4024) The DMACSoftSReq Register is read/write and enables DMA single transfer requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit.
Page 600: Dma Configuration Register (Dmacconfig - 0X5000 4030)
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 556. DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C) Name Function 15:0 SoftLSReq Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect.
Page 601: Dma Request Select Register (Dmareqsel - 0X400F C1C4)
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.5.15 DMA Request Select register (DMAReqSel - 0x400F C1C4) DMAReqSel is a read/write register that allows selecting between UART or Timer DMA requests for DMA inputs 8 through 15. Table 559 shows the bit assignments of the DMAReqSel Register.
Page 602: Dma Channel Source Address Registers (Dmaccxsrcaddr - 0X5000 41X0)
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.5.17 DMA Channel Source Address registers (DMACCxSrcAddr - 0x5000 41x0) The eight read/write DMACCxSrcAddr Registers (DMACC0SrcAddr to DMACC7SrcAddr) contain the current source address (byte-aligned) of the data to be transferred. Each register is programmed directly by software before the appropriate channel is enabled.
Page 603: Dma Channel Control Registers (Dmaccxcontrol - 0X5000 41Xc)
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 562. DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8) Name Function Reserved, and must be written as 0. 31:2 Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
Page 604 UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 563. DMA channel control registers (DMACCxControl - 0x5000 41xC) Name Function 11:0 TransferSize Transfer size. This field sets the size of the transfer. The transfer size value must be set before the channel is enabled.
Page 605: Dma Channel Configuration Registers (Dmaccxconfig - 0X5000 41X0)
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 563. DMA channel control registers (DMACCxControl - 0x5000 41xC) …continued Name Function Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.
Page 606 UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 564. DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0) Name Function Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled.
Page 607: Lock Control
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.5.21.1 Lock control The lock control may set the lock bit by writing a 1 to bit 16 of the DMACCxConfig Register. When a burst occurs, the AHB arbiter will not de-grant the master during the burst until the lock is de-asserted.
Page 608: Using The Dma Controller
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.6 Using the DMA controller 31.6.1 Programming the DMA controller All accesses to the DMA Controller internal register must be word (32-bit) reads and writes. 31.6.1.1 Enabling the DMA controller To enable the DMA controller set the Enable bit in the DMACConfig register.
Page 609: Halting A Dma Channel
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 1. Read the DMACEnbldChns controller register and find out which channels are inactive. 2. Choose an inactive channel that has the required priority. 3. Program the DMA controller 31.6.1.6 Halting a DMA channel Set the halt bit in the relevant DMA channel configuration register.
Page 610: Peripheral-To-Memory Or Memory-To-Peripheral Dma Flow
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Table 566. DMA request signal usage Transfer direction Request generator Flow controller Memory-to-peripheral Peripheral DMA Controller Peripheral-to-memory Peripheral DMA Controller Memory-to-memory DMA Controller DMA Controller Source peripheral to destination peripheral...
Page 611: Memory-To-Memory Dma Flow
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 7. When the destination DMA request goes active and there is data in the DMA Controller FIFO, transfer data into the destination peripheral. 8. If an error occurs while transferring the data, an error interrupt is generated, the DMA stream is disabled, and the flow sequence ends.
Page 612: Hardware Interrupt Sequence Flow
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.6.3.1 Hardware interrupt sequence flow When a DMA interrupt request occurs, the Interrupt Service Routine needs to: 1. Read the DMACIntTCStat Register to determine whether the interrupt was generated due to the end of the transfer (terminal count). A 1 bit indicates that the transfer completed.
Page 613: Linked List Items
UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) 31.6.5.1 Linked list items A Linked List Item (LLI) consists of four words. These words are organized in the following order: 1. DMACCxSrcAddr. 2. DMACCxDestAddr. 3. DMACCxLLI. 4. DMACCxControl. Note: The DMACCxConfig DMA channel Configuration Register is not part of the linked list item.
Page 614 UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) Linked List Array LLI1 Source address = 0x 2002 A200 0x2002 0000 Destination address = peripheral 0x2002 A200 Next LLI address = 0x2002 0010 Control information = length 3072 3072 bytes of data...
Page 615 UM10360 NXP Semiconductors Chapter 31: LPC176x/5x General Purpose DMA (GPDMA) • Source start address 0x2003 1200. • Destination address set to the destination peripheral address. • Transfer width, word (32-bit). • Transfer size, 3072 bytes (0xC00). • Source and destination burst sizes, 16 transfers.
Page 616: Chapter 32: Lpc176X/5X Flash Memory Interface And Programming
UM10360 Chapter 32: LPC176x/5x Flash memory interface and programming Rev. 3 — 19 December 2013 User manual 32.1 Introduction The boot loader controls initial operation after reset and also provides the tools for programming the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system.
Page 617: Memory Map After Any Reset
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming A hardware flash signature generation capability is built into the flash memory. this feature can be used to create a signature that can then be used to verify flash contents. Details of...
Page 618: Communication Protocol
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming sends an ASCII string ("Synchronized<CR><LF>") to the host. In response to this the host should send the same string ("Synchronized<CR><LF>"). The auto-baud routine looks at the received characters to verify synchronization. If synchronization is verified then "OK<CR><LF>"...
Page 619: Isp Flow Control
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.3.2.4 ISP flow control A software XON/XOFF flow control scheme is used to prevent data loss due to buffer overrun. When the data arrives rapidly, the ASCII control character DC3 (0x13) is sent to stop the flow of data.
Page 620: Boot Process Flowchart
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.4 Boot process flowchart RESET INITIALIZE CRP1/2/3 ENABLED? ENABLE DEBUG WATCHDOG FLAG SET? USER CODE VALID? CRP3 ENABLED? EXECUTE INTERNAL USER CODE Enter ISP USER CODE VALID? MODE? (P2.10=LOW)
Page 621: Sector Numbers
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.5 Sector numbers Some IAP and ISP commands operate on "sectors" and specify sector numbers. The following table indicate the correspondence between sector numbers and memory addresses for LPC176x/5x devices containing 32, 64, 128, 256 and 512 kB of flash respectively.
Page 622: Code Read Protection (Crp)
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.6 Code Read Protection (CRP) Code Read Protection is a mechanism that allows user to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted.
Page 623 UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming Table 569. Code Read Protection hardware/software interaction CRP option User Code P2.10 pin at JTAG enabled LPC176x/5x partial flash Valid reset enters ISP update in ISP mode mode None...
Page 624: Isp Commands
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.7 ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
Page 625: Set Baud Rate
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.7.2 Set Baud Rate <Baud Rate> <stop bit> Table 572. ISP Set Baud Rate command Command Input Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 | 230400...

Page 626: Read Memory

UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming The ISP command handler compares it with the check-sum of the received bytes. If the check-sum matches, the ISP command handler responds with "OK<CR><LF>" to continue further transmission. If the check-sum does not match, the ISP command handler responds with "RESEND<CR><LF>".

Page 627: Prepare Sector(S) For Write Operation
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.7.6 Prepare sector(s) for write operation <start sector number> <end sector number> This command makes flash write/erase operation a two step process. Table 577. ISP Prepare sector(s) for write operation command...

Page 628: Go

UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.7.8 Go <address> <mode> Table 579. ISP Go command Command Input Address: Flash or RAM address from which the code execution is to be started. This address should be on a word boundary.

Page 629: Blank Check Sector(S)
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.7.10 Blank check sector(s) <sector number> <end sector number> Table 581. ISP Blank check sector command Command Input Start Sector Number: End Sector Number: Should be greater than or equal to start sector number.

Page 630: Read Boot Code Version Number
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.7.12 Read Boot Code version number Table 584. ISP Read Boot Code version number command Command Input None Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format.
Page 631: Isp Return Codes
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.7.15 ISP Return Codes Table 587. ISP Return Codes Summary Return Mnemonic Description Code CMD_SUCCESS Command is executed successfully. Sent by ISP handler only when command given by the host has been completely and successfully executed.
Page 632: Iap Commands
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.8 IAP commands For in-application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. The result from the IAP command is returned in the table pointed to by register r1.
Page 633 UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming Note that the first entry in the command table is the IAP command, followed by any required command parameters, starting with Param0. The first entry in the output table is the Return Code, followed by any other results, starting with Result0.
Page 634: Prepare Sector(S) For Write Operation
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming COMMAND CODE command PARAMETER 1 parameter table PARAMETER 2 ARM REGISTER r0 PARAMETER n ARM REGISTER r1 STATUS CODE RESULT 1 command result table RESULT 2 RESULT n Fig 138. IAP parameter passing 32.8.1 Prepare sector(s) for write operation...
Page 635: Copy Ram To Flash
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.8.2 Copy RAM to Flash Table 590. IAP Copy RAM to Flash command Command Copy RAM to Flash Input Command code: 51 (decimal) Param0(DST): Destination flash address where data bytes are to be written. This address should be a 256 byte boundary.
Page 636: Blank Check Sector(S)
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.8.4 Blank check sector(s) Table 592. IAP Blank check sector(s) command Command Blank check sector(s) Input Command code: 53 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).
Page 637: Read Device Serial Number
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.8.7 Read device serial number Table 595. IAP Read device serial number command Command Read device serial number Input Command code: 58 (decimal) Parameters: None Return Code CMD_SUCCESS |...
Page 638: Iap Status Codes
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming Table 597. Re-invoke ISP Command Compare Return Code None Result None. Description This command is used to invoke the boot loader in ISP mode. It maps boot vectors, sets PCLK = CCLK / 4, configures UART0 pins Rx and Tx, resets...
Page 639: Flash Signature Generation
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.10 Flash signature generation The flash module contains a built-in signature generator. This generator can produce a 128-bit signature from a range of flash memory. A typical usage is to verify the flashed contents against a calculated signature (e.g.
Page 640: Registers
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.10.1.1 Signature generation address and control registers These registers control automatic signature generation. A signature can be generated for any part of the flash memory contents. The address range to be used for generation is defined by writing the start address to the signature start address register (FMSSTART) and the stop address to the signature stop address register (FMSSTOP.
Page 641: 0X0X4008 4Fe0)
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming Table 604. FMSW2 register bit description (FMSW2, address: 0x4008 4034) Symbol Description Reset Value 31:0 SW2[95:64] Word 2 of 128-bit signature (bits 95 to 64). Table 605. FMSW3 register bit description (FMSW3, address: 0x4008 4038)
Page 642: Algorithm And Procedure For Signature Generation
UM10360 NXP Semiconductors Chapter 32: LPC176x/5x Flash memory interface and programming 32.10.2 Algorithm and procedure for signature generation Signature generation A signature can be generated for any part of the flash contents. The address range to be used for signature generation is defined by writing the start address to the FMSSTART register, and the stop address to the FMSSTOP register.
Page 643: Features
UM10360 Chapter 33: LPC176x/5x JTAG, Serial Wire Debug (SWD), and Trace Rev. 3 — 19 December 2013 User manual 33.1 Features • Supports both standard JTAG and ARM Serial Wire Debug modes. • Direct debug access to all memories, registers, and peripherals. •...
Page 644: Debug Notes
UM10360 NXP Semiconductors Chapter 33: LPC176x/5x JTAG, Serial Wire Debug (SWD), and Trace Table 608. JTAG pin description Pin Name Type Description Input JTAG Test Clock. This pin is the clock for debug logic when in the JTAG debug mode.
Page 645: Debug Memory Re-Mapping
UM10360 NXP Semiconductors Chapter 33: LPC176x/5x JTAG, Serial Wire Debug (SWD), and Trace Another issue is that debug mode changes the way in which reduced power modes are handled by the Cortex-M3 CPU. This causes power modes at the device level to be different from normal modes operation.
Page 646: Arm Cortex-M3 User Guide: Introduction
UM10360 Chapter 34: Appendix: Cortex-M3 user guide Rev. 3 — 20 December 2013 User manual 34.1 ARM Cortex-M3 User Guide: Introduction The material in this appendix is provided by ARM Limited for inclusion in the User Manuals of devices containing the Cortex-M3 CPU. Minimal changes have been made to reflect implementation options and other distinctions that apply specifically to LPC176x/5x devices.
Page 647: System Level Interface
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb instruction set, ensuring high code density and reduced program memory requirements.
Page 648: Cortex-M3 Processor Features And Benefits Summary
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide LPC176x/5x devices support JTAG and Serial Wire Debug, Serial Wire Viewer, and include the Embedded Trace Macrocell. See Section 33.1 for additional information. 34.1.1.3 Cortex-M3 processor features and benefits summary •...
Page 649: Arm Cortex-M3 User Guide: Instruction Set
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2 ARM Cortex-M3 User Guide: Instruction Set 34.2.1 Instruction set summary The processor implements a version of the Thumb instruction set. Table 612 lists the supported instructions. Note Table 612: •...
Page 650 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 612. Cortex-M3 instructions …continued Mnemonic Operands Brief description Flags Page Instruction Synchronization Barrier Section 34.2.10.5 If-Then condition block Section 34.2.9.3 Load Multiple registers, increment after Section 34.2.4.6 Rn{!}, reglist Load Multiple registers, decrement before Section 34.2.4.6...
Page 651 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 612. Cortex-M3 instructions …continued Mnemonic Operands Brief description Flags Page Signed Divide Section 34.2.6.3 SDIV {Rd,} Rn, Rm Send Event Section 34.2.10.9 Signed Multiply with Accumulate (32 x 32 + 64), Section 34.2.6.2...
Page 652: Intrinsic Functions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.2 Intrinsic functions ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, you might have to use inline assembler to access some instructions.
Page 653: Operands
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • Section 34.2.3.1 “Operands” • Section 34.2.3.2 “Restrictions when using PC or SP” • Section 34.2.3.3 “Flexible second operand” • Section 34.2.3.4 “Shift Operations” • Section 34.2.3.5 “Address alignment” • Section 34.2.3.6 “PC-relative expressions”...
Page 654: Register With Optional Shift
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Remark: In the constants shown above, X and Y are hexadecimal digits. In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions.
Page 655: Asr
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or Section 34.2.3.3. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the various shift operations and how they affect the carry flag.
Page 656: Lsl
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • If n is 33 or more and the carry flag is updated, it is updated to 0. Fig 142. LSR#3 34.2.3.4.3 LSL Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result.
Page 657: Rrx
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm.
Page 658: Pc-Relative Expressions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses, see Section 34.4.3.8 “Configuration and Control Register”. 34.2.3.6 PC-relative expressions A PC-relative expression or label is a symbol that represents the address of an instruction or literal data.
Page 659: The Condition Flags
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide This section describes: • Section 34.2.3.7.1 “The condition flags” • Section 34.2.3.7.2 “Condition code suffixes”. 34.2.3.7.1 The condition flags The APSR contains the following condition flags: N — Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Page 660: Instruction Width Selection
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 615. Condition code suffixes Suffix Flags Meaning C = 1 and Z = 0 Higher, unsigned > Lower or same, unsigned  C = 0 or Z = 1 Greater than or equal, signed ...
Page 661: Memory Access Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4 Memory access instructions Table 616 shows the memory access instructions: Table 616. Memory access instructions Mnemonic Brief description Load PC-relative address Section 34.2.4.1 Clear Exclusive Section 34.2.4.9 CLREX Load Multiple registers Section 34.2.4.6...
Page 662: Adr
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.1 ADR Load PC-relative address. 34.2.4.1.1 Syntax ADR{cond} Rd, label where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rd is the destination register. label is a PC-relative expression. See Section 34.2.3.6 “PC-relative...
Page 663: Ldr And Str, Immediate Offset
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.2 LDR and STR, immediate offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. 34.2.4.2.1 Syntax op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset op{type}{cond} Rt, [Rn, #offset]! ;...
Page 664: Restrictions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide [Rn, #offset] • Pre-indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn.
Page 665: Examples
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.2.5 Examples R8, [R10] ; Loads R8 from the address in R10. LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word ; 960 bytes above the address in R5, and ;...
Page 666: Ldr And Str, Register Offset
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.3 LDR and STR, register offset Load and Store with register offset. 34.2.4.3.1 Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR: Load Register. STR: Store Register.
Page 667: Condition Flags
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block.
Page 668: Ldr And Str, Unprivileged
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.4 LDR and STR, unprivileged Load and Store with unprivileged access. 34.2.4.4.1 Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR: Load Register. STR: Store Register.
Page 669: Examples
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.4.5 Examples STRBTEQ R4, [R7] ; Conditionally store least significant byte in ; R4 to an address in R7, with unprivileged access LDRHT R2, [R2, #8] ; Load halfword value from an address equal to ;...
Page 670: Ldr, Pc-Relative
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.5 LDR, PC-relative Load register from memory. 34.2.4.5.1 Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words type is one of: B: unsigned byte, zero extend to 32 bits on loads.
Page 671: Condition Flags
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address • if the instruction is conditional, it must be the last instruction in the IT block.
Page 672: Ldm And Stm
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.6 LDM and STM Load and Store Multiple registers. 34.2.4.6.1 Syntax op{addr_mode}{cond} Rn{!}, reglist where: op is one of: LDM: Load Multiple registers. STM: Store Multiple registers. addr_mode is any one of the following: IA: Increment address After each access.
Page 673: Restrictions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist.
Page 674: Push And Pop
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. 34.2.4.7.1 Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”.
Page 675: Ldrex And Strex
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.8 LDREX and STREX Load and Store Register Exclusive. 34.2.4.8.1 Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn]...
Page 676: Condition Flags
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • do not use PC • do not use SP for Rd and Rt • for STREX, Rd must be different from both Rt and Rn • the value of offset must be a multiple of four in the range 0-1020.
Page 677: Clrex
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.4.9 CLREX Clear Exclusive. 34.2.4.9.1 Syntax CLREX{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.4.9.2 Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store.
Page 678: General Data Processing Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5 General data processing instructions Table 619 shows the data processing instructions: Table 619. Data processing instructions Mnemonic Brief description Add with Carry Section 34.2.5.1 Section 34.2.5.1 Section 34.2.5.1 ADDW Logical AND Section 34.2.5.2...
Page 679: Add, Adc, Sub, Sbc, And Rsb
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. 34.2.5.1.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only...
Page 680: Note
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide – Rn must also be SP – any shift in Operand2 must be limited to a maximum of 3 bits using LSL • Rn can be SP only in ADD and SUB •...
Page 681 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 96-bit subtraction: SUBS R6, R6, R9 ; subtract the least significant words SBCS R9, R2, R1 ; subtract the middle words with carry R2, R8, R11 ; subtract the most significant words with carry UM10360 All information provided in this document is subject to legal disclaimers.
Page 682: And, Orr, Eor, Bic, And Orn
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. 34.2.5.2.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND: logical AND.
Page 683 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide EORS R7, R11, #0x18181818 R0, R1, #0xab R7, R11, R14, ROR #4 ORNS R7, R11, R14, ASR #32 UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Page 684: Asr, Lsl, Lsr, Ror, And Rrx
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. 34.2.5.3.1 Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n...
Page 685: Condition Flags
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.3.4 Condition flags If S is specified: • these instructions update the N and Z flags according to the result • the C flag is updated to the last bit shifted out, except when the shift length is 0, see Section 34.2.3.4 “Shift...
Page 686: Clz
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.4 CLZ Count Leading Zeros. 34.2.5.4.1 Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see Section 34.2.3.7. Rd is the destination register. Rm is the operand register. 34.2.5.4.2 Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd.
Page 687: Cmp And Cmn
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.5 CMP and CMN Compare and Compare Negative. 34.2.5.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see Section 34.2.3.7. Rn is the register holding the first operand.
Page 688: Mov And Mvn
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.6 MOV and MVN Move and Move NOT. 34.2.5.6.1 Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result...
Page 689: Restrictions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.6.3 Restrictions You can use SP and PC only in the MOV instruction, with the following restrictions: • the second operand must be a register without shift • you must not specify the S suffix.
Page 690: Movt
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.7 MOVT Move Top. 34.2.5.7.1 Syntax MOVT{cond} Rd, #imm16 where: cond is an optional condition code, see Section 34.2.3.7. Rd is the destination register. imm16 is a 16-bit immediate constant. 34.2.5.7.2 Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register.
Page 691: Rev, Rev16, Revsh, And Rbit
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. 34.2.5.8.1 Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently.
Page 692: Tst And Teq
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.5.9 TST and TEQ Test bits and Test Equivalence. 34.2.5.9.1 Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rn is the register holding the first operand.
Page 693: Multiply And Divide Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6 Multiply and divide instructions Table 620 shows the multiply and divide instructions: Table 620. Multiply and divide instructions Mnemonic Brief description Multiply with Accumulate, 32-bit result Section 34.2.6.1 Multiply and Subtract, 32-bit result Section 34.2.6.1...
Page 694: Mul, Mla, And Mls
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. 34.2.6.1.1 Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ;...
Page 695: Examples
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.1.5 Examples R10, R2, R5 ; Multiply, R10 = R2 x R5 R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5 MULS R0, R2, R2 ;...
Page 696: Umull, Umlal, Smull, And Smlal
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.2 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. 34.2.6.2.1 Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL: Unsigned Long Multiply.
Page 697: Examples
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.2.5 Examples UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6 SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8 UM10360 All information provided in this document is subject to legal disclaimers.
Page 698: Sdiv And Udiv
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.6.3 SDIV and UDIV Signed Divide and Unsigned Divide. 34.2.6.3.1 Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”.
Page 699: Saturating Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.7 Saturating instructions This section describes the saturating instructions, SSAT and USAT. 34.2.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. 34.2.7.1.1 Syntax...
Page 700: Restrictions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • otherwise, the result returned is the same as the value to be saturated. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the instruction sets the Q flag to 1 in the APSR.
Page 701: Bitfield Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8 Bitfield instructions Table 621 shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 621. Packing and unpacking instructions Mnemonic Brief description Bit Field Clear Section 34.2.8.1...
Page 702: Bfc And Bfi
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8.1 BFC and BFI Bit Field Clear and Bit Field Insert. 34.2.8.1.1 Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”.
Page 703: Sbfx And Ubfx
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. 34.2.8.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see Section 34.2.3.7 “Conditional...
Page 704: Sxt And Uxt
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8.3 SXT and UXT Sign extend and Zero extend. 34.2.8.3.1 Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B: Extends an 8-bit value to a 32-bit value.
Page 705: Examples
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.8.3.5 Examples SXTH R4, R6, ROR #16 ; Rotate R6 right by 16 bits, then obtain the lower ; halfword of the result and then sign extend to ; 32 bits and write the result to R4.
Page 706: Branch And Control Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9 Branch and control instructions Table 622 shows the branch and control instructions: Table 622. Branch and control instructions Mnemonic Brief description Branch Section 34.2.9.1 Branch with Link Section 34.2.9.1 Branch indirect with Link Section 34.2.9.1...
Page 707: B, Bl, Bx, And Blx
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.1 B, BL, BX, and BLX Branch instructions. 34.2.9.1.1 Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register).
Page 708: Restrictions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.1.3 Restrictions The restrictions are: • do not use PC in the BLX instruction • for BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0 •...
Page 709: Cbz And Cbnz
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. 34.2.9.2.1 Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination.
Page 710: Syntax
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.3 IT If-Then condition instruction. 34.2.9.3.1 Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block.
Page 711: Condition Flags
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • CPSID and CPSIE. Other restrictions when using an IT block are: • a branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are: –...
Page 712 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide ; Next instruction is conditional R0, R0, R1 ; Syntax error: no condition code used in IT block UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Page 713: Tbb And Tbh
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.9.4 TBB and TBH Table Branch Byte and Table Branch Halfword. 34.2.9.4.1 Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths.
Page 714 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the ; branch table BranchTable_H ((CaseA - BranchTable_H)/2) ; CaseA offset calculation ((CaseB - BranchTable_H)/2) ; CaseB offset calculation ((CaseC - BranchTable_H)/2) ;...
Page 715: Miscellaneous Instructions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10 Miscellaneous instructions Table 624 shows the remaining Cortex-M3 instructions: Table 624. Miscellaneous instructions Mnemonic Brief description Breakpoint Section 34.2.10.1 BKPT Change Processor State, Disable Interrupts Section 34.2.10.2 CPSID Change Processor State, Enable Interrupts Section 34.2.10.2...
Page 716: Bkpt
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.1 BKPT Breakpoint. 34.2.10.1.1 Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 34.2.10.1.2 Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
Page 717: Cps
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.2 CPS Change Processor State. 34.2.10.2.1 Syntax CPSeffect iflags where: effect is one of: IE Clears the special purpose register. ID Sets the special purpose register iflags is a sequence of one or more flags: i Set or clear PRIMASK.
Page 718: Dmb
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.3 DMB Data Memory Barrier. 34.2.10.3.1 Syntax DMB{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.3.2 Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction.
Page 719: Dsb
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.4 DSB Data Synchronization Barrier. 34.2.10.4.1 Syntax DSB{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.4.2 Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes.
Page 720: Isb
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.5 ISB Instruction Synchronization Barrier. 34.2.10.5.1 Syntax ISB{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.5.2 Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed.
Page 721: Mrs
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.6 MRS Move the contents of a special register to a general-purpose register. 34.2.10.6.1 Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. Rd is the destination register.
Page 722: Msr
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.7 MSR Move the contents of a general-purpose register into the specified special register. 34.2.10.7.1 Syntax MSR{cond} spec_reg, Rn where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”.
Page 723: Nop
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.8 NOP No Operation. 34.2.10.8.1 Syntax NOP{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.8.2 Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage.
Page 724: Sev
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.9 SEV Send Event. 34.2.10.9.1 Syntax SEV{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.9.2 Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system.
Page 725: Svc
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.10 SVC Supervisor Call. 34.2.10.10.1 Syntax SVC{cond} #imm where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. imm is an expression evaluating to an integer in the range 0-255 (8-bit value).
Page 726: Wfe
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.11 WFE Wait For Event. 34.2.10.11.1 Syntax WFE{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution” 34.2.10.11.2 Operation WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs: •...
Page 727: Wfi
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.2.10.12 WFI Wait for Interrupt. 34.2.10.12.1 Syntax WFI{cond} where: cond is an optional condition code, see Section 34.2.3.7 “Conditional execution”. 34.2.10.12.2 Operation WFI is a hint instruction that suspends execution until one of the following events occurs: •...
Page 728: Arm Cortex-M3 User Guide: Processor
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3 ARM Cortex-M3 User Guide: Processor 34.3.1 Programmers model This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks.
Page 729: Core Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 625. Summary of processor mode, execution privilege level, and stack use options Processor Used to Privilege level for Stack used mode execute software execution Thread Applications Privileged or Main stack or process...
Page 730: General-Purpose Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 626. Core register set summary …continued Name Type Required Reset Description privilege value EPSR Privileged Table 630 0x01000000 PRIMASK Privileged Table 631 0x00000000 FAULTMASK Privileged Table 632 0x00000000 BASEPRI Privileged...
Page 731 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The PSR bit assignments are: Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: •...
Page 732 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 628. APSR bit assignments Bits Name Function [31] Negative or less than flag: 0 = operation result was positive, zero, greater than, or equal 1 = operation result was negative or less than.
Page 733 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 629. IPSR bit assignments Bits Name Function [31:9] Reserved [8:0] ISR_NUMBER This is the number of the current exception: 0 = Thread mode 1 = Reserved 2 = NMI 3 = Hard fault...
Page 734: Exception Mask Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Interruptible-continuable instructions: When an interrupt occurs during the execution of an LDM or STM instruction, the processor: After servicing the interrupt, the processor: • stops the load multiple or store multiple instruction operation temporarily.
Page 735: Control Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 633. BASEPRI register bit assignments Bits Name Function [31:8] Reserved [7:0] BASEPRI Priority mask bits: 0x0000 = no effect Nonzero = defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI.
Page 736: Data Types
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The NVIC registers control interrupt handling. See Section 34.4.2 “Nested Vectored Interrupt Controller” for more information. 34.3.1.5 Data types The processor: • supports the following data types: – 32-bit words – 16-bit halfwords –...
Page 737: Memory Model
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.2 Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: The regions for SRAM and peripherals include bit-band regions.
Page 738: Memory System Ordering Of Memory Accesses
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • Normal: The processor can re-order transactions for efficiency, or perform speculative reads. • Device: The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. • Strongly-ordered: The processor preserves transaction order relative to all other transactions.
Page 739: Behavior Of Memory Accesses
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide ‘<‘ means that accesses are observed in program order, that is, A1 is always observed before A2. 34.3.2.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 635.
Page 740: Bit-Banding
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See Section 34.2.10.3 “DMB”. • The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute.
Page 741 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The memory map has two 32MB alias regions that map to two 1MB bit-band regions: • accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as...
Page 742: Directly Accessing An Alias Region
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + (7*4). • The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 = 0x22000000 + (0*32) + (0 *4).
Page 743: Memory Endianness
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.2.6 Memory endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word.
Page 744: Programming Hints For The Synchronization Primitives
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location.
Page 745 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide __ldrex((volatile char *) 0xFF); UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. User manual Rev. 3 — 20 December 2013...
Page 746: Exception Model
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.3 Exception model This section describes the exception model. 34.3.3.1 Exception states Each exception is in one of the following states: • Inactive The exception is not active and not pending.
Page 747 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide A memory management fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled.
Page 748: Exception Handlers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 639. Properties of the different exception types Exception Exception Priority Vector address Activation number number type or offset Bus fault Configurable Synchronous when 0x00000014 precise, asynchronous when imprecise Usage fault...
Page 749: Vector Table
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.3.4 Vector table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 148 shows the order of the exception vectors in the vector table.
Page 750: Interrupt Priority Grouping
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • Section 34.4.3.9 “System Handler Priority Registers” • Section 34.4.2.7 “Interrupt Priority Registers”. Remark: Configurable priority values are in the range 0 to 31. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception.
Page 751: Exception Entry
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide – there is no pending exception with sufficient priority to be serviced – the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.
Page 752: Exception Return
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes.
Page 753 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 640. Exception return behavior …continued EXC_RETURN[3:0] Description b1001 Return to Thread mode. Exception return gets state from MSP. Execution uses MSP after return. b1101 Return to Thread mode. Exception return gets state from PSP.
Page 754: Fault Handling
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.4 Fault handling Faults are a subset of the exceptions, see Section 34.3.3. The following generate a fault: • a bus error on: – an instruction fetch or vector table load –...
Page 755: Fault Escalation And Hard Faults
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.4.2 Fault escalation and hard faults All faults exceptions except for hard fault have configurable exception priority, see Section 34.4.3.9 “System Handler Priority Registers”. Software can disable execution of the handlers for these faults, see Section 34.4.3.10 “System Handler Control and State...
Page 756: Lockup
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.4.4 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in lockup state it does not execute any instructions.
Page 757: Power Management
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.5 Power management Note: NXP devices based on the Cortex-M3 processor, including the LPC176x/5x, support additional reduced power modes. See Section 4.8 “Power control” information on all available reduced power modes.
Page 758: Sleep-On-Exit
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.3.5.1.3 Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an exception handler it returns to Thread mode and immediately enters sleep mode.
Page 759: Power Management Programming Hints
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Remark: If the processor detects a connection to a debugger it disables the WIC. 34.3.5.4 Power management programming hints ANSI C cannot directly generate the WFI and WFE instructions. The CMSIS provides the...
Page 760: Arm Cortex-M3 User Guide: Peripherals
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4 ARM Cortex-M3 User Guide: Peripherals 34.4.1 About the Cortex-M3 peripherals The address map of the Private peripheral bus (PPB) is: Table 643. Core peripheral register regions Address Core peripheral Description...
Page 761: Nested Vectored Interrupt Controller
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.2 Nested Vectored Interrupt Controller This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: • Up to 112 interrupts. The number of interrupts implemented is device dependent.
Page 762: Interrupt Set-Enable Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. For more information see the description of the NVIC_SetPriority function in Section 34.4.2.10.1 “NVIC programming hints”. Table 645...
Page 763: Interrupt Set-Pending Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 647. ICER bit assignments Bits Name Function [31:0] CLRENA Interrupt clear-enable bits. Write: 0 = no effect 1 = disable interrupt. Read: 0 = interrupt disabled 1 = interrupt enabled.
Page 764: Interrupt Active Bit Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 649. ICPR bit assignments Bits Name Function [31:0] CLRPEND Interrupt clear-pending bits. Write: 0 = no effect 1 = removes pending state an interrupt. Read: 0 = interrupt is not pending 1 = interrupt is pending.
Page 765: Software Trigger Interrupt Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 651. IPR bit assignments Bits Name Function [31:24] Priority, byte offset 3 Each priority field holds a priority value, 0-31. The lower the value, the greater the priority of the corresponding interrupt.
Page 766: Hardware And Software Control Of Interrupts
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide When the processor enters the ISR, it automatically removes the pending state from the interrupt, see Section 34.4.2.9.1. For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again.
Page 767: Nvic Programming Hints
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.2.10.1 NVIC programming hints Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts...
Page 768: System Control Block
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.3 System control block The System control block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. The system control block registers are: Table 654.
Page 769: About It Folding
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 655. ACTLR bit assignments Bits Name Function [31:3] Reserved DISFOLD When set to 1, disables IT folding. see Section 34.4.3.2.1 for more information. DISDEFWBUF When set to 1, disables write buffer use during default memory map accesses.
Page 770 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide – whether there are preempted active exceptions – the exception number of the highest priority pending exception – whether any interrupts are pending. See the register summary in Table 654, and the Type descriptions in...
Page 771: Vector Table Offset Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 657. ICSR bit assignments …continued Bits Name Type Function [25] PENDSTCLR SysTick exception clear-pending bit. Write: 0 = no effect 1 = removes the pending state from the SysTick exception.
Page 772: Application Interrupt And Reset Control Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 658. VTOR bit assignments Bits Name Function [31:30] Reserved. [29:8] TBLOFF Vector table base offset field. It contains bits[29:8] of the offset of the table base from the bottom of the memory map.
Page 773: Binary Point
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 659. AIRCR bit assignments …continued Bits Name Type Function SYSRESETREQ System reset request: 0 = no system reset request 1 = asserts a signal to the outer system that requests a reset.
Page 774: Configuration And Control Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 661. SCR bit assignments Bits Name Function [31:5] Reserved. SEVONPEND Send Event on Pending bit: 0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1 = enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
Page 775: System Handler Priority Registers
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 662. CCR bit assignments Bits Name Function [31:10] Reserved. STKALIGN Indicates stack alignment on exception entry: 0 = 4-byte aligned 1 = 8-byte aligned. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment.
Page 776: System Handler Priority Register 1
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 663. System fault handler priority fields Handler Field Register description Memory management fault PRI_4 Table 664 Bus fault PRI_5 Usage fault PRI_6 SVCall PRI_11 Table 665 PendSV PRI_14 Table 666...
Page 777: Caution
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 667. SHCSR bit assignments Bits Name Function [31:19] Reserved [18] USGFAULTENA Usage fault enable bit, set to 1 to enable [17] BUSFAULTENA Bus fault enable bit, set to 1 to enable...
Page 778: Configurable Fault Status Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.3.11 Configurable Fault Status Register The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register summary in Table 654 for its attributes. The bit assignments are: Fig 149.
Page 779: Bus Fault Status Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 668. MMFSR bit assignments …continued Bits Name Function MUNSTKERR Memory manager fault on unstacking for a return from exception: 0 = no unstacking fault 1 = unstack for an exception return has caused one or more access violations.
Page 780: Usage Fault Status Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 669. BFSR bit assignments …continued Bits Name Function STKERR Bus fault on stacking for exception entry: 0 = no stacking fault 1 = stacking for an exception entry has caused one or more bus faults.
Page 781 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 670. UFSR bit assignments Bits Name Function [15:10] Reserved. DIVBYZERO Divide by zero usage fault: 0 = no divide by zero fault, or divide by zero trapping not enabled 1 = the processor has executed an SDIV or UDIV instruction with a divisor of 0.
Page 782: Hard Fault Status Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.3.12 Hard Fault Status Register The HFSR gives information about events that activate the hard fault handler. See the register summary in Table 654 for its attributes. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
Page 783: System Control Block Design Hints And Tips
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 673. BFAR bit assignments Bits Name Function [31:0] ADDRESS When the BFARVALID bit of the BFSR is set to 1, this field holds the address of the location that generated the bus fault When an unaligned access faults the address in the BFAR is the one requested by the instruction, even if it is not the address of the fault.
Page 784: System Timer, Systick
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.4 System timer, SysTick The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then counts down on subsequent clocks.
Page 785: Systick Reload Value Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.4.2 SysTick Reload Value Register The LOAD register specifies the start value to load into the VAL register. See the register summary in Table 674 for its attributes. The bit assignments are shown in Table 676.
Page 786: Systick Design Hints And Tips
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide If a different frequency is used than that intended by the factory preset value, calculate the calibration value required from the frequency of the processor clock or external clock. 34.4.4.5 SysTick design hints and tips The SysTick counter runs on the processor clock.
Page 787: Memory Protection Unit
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.5 Memory protection unit This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: •...
Page 788: Mpu Type Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 679. Memory attributes summary …continued Memory type Shareability Other attributes Description Non-shared Memory-mapped peripherals that only a single processor uses. Normal Shared Non-cacheable Normal memory that is shared Write-through between several processors.
Page 789: Mpu Control Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 681. TYPE register bit assignments …continued Bits Name Function [15:8] DREGION Indicates the number of supported MPU data regions: 0x08 = Eight MPU regions. [7:0] Reserved. SEPARATE Indicates support for unified or separate instruction and date memory maps: 0 = unified.
Page 790: Mpu Region Number Register
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide • For privileged accesses, the default memory map is as described in Section 34.3.2 “Memory model”. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map.
Page 791: The Addr Field
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 684. RBAR bit assignments [31:N] ADDR Region base address field. The value of N depends on the region size. For more information see Section 34.4.5.4.1. [(N-1):5] Reserved. VALID MPU Region Number valid bit:...
Page 792: Size Field Values
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 685. RASR bit assignments Bits Name Function [31:29] Reserved. [28] Instruction access disable bit: 0 = instruction fetches enabled 1 = instruction fetches disabled. [27] Reserved. [26:24] Access permission field, see Table 689.
Page 793: Mpu Access Permission Attributes
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.4.5.6 MPU access permission attributes This section describes the MPU access permission attributes. The access permission bits, TEX, C, B, S, AP, and XN, of the RASR, control access to the corresponding memory region.
Page 794: Mpu Mismatch
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Table 689. AP encoding AP[2:0] Privileged Unprivileged Description permissions permissions No access No access All accesses generate a permission fault No access Access from privileged software only Writes by unprivileged software generate a...
Page 795: Writes
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ;...
Page 796: Subregions
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Use an STM instruction to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ;...
Page 797: Mpu Design Hints And Tips
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Fig 150. SRD example 34.4.5.9 MPU design hints and tips To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: •...
Page 798: Arm Cortex-M3 User Guide: Glossary
UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide 34.5 ARM Cortex-M3 User Guide: Glossary Abort — A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory.
Page 799 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Condition field — A four-bit field in an instruction that specifies a condition under which the instruction can execute. Context — The environment that each process operates in for a multitasking operating system.
Page 800 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Index register — In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory.
Page 801 UM10360 NXP Semiconductors Chapter 34: Appendix: Cortex-M3 user guide Should Be Zero or Preserved (SBZP) — Write as 0, or all 0s for bit fields, by software, or preserved by writing the same value back that has been previously read from the same field on the same processor.
Page 802: Abbreviations
UM10360 Chapter 35: Supplementary information Rev. 3 — 20 December 2013 User manual 35.1 Abbreviations Table 691. Abbreviations Acronym Description Analog-to-Digital Converter Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel Direct Memory Access Digital Signal Processing...
Page 803: Legal Information
NXP Semiconductors. applications and products. In no event shall NXP Semiconductors be liable for any indirect, incidental, NXP Semiconductors does not accept any liability related to any default, punitive, special or consequential damages (including - without limitation - lost...
Page 804: Tables
UM10360 NXP Semiconductors Chapter 35: Supplementary information 35.3 Tables Table 1. Ordering information .....8 Table 36. PLL1 Divider values ....54 Table 2.
Page 805 UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 67. Interrupt Priority Register 5 (IPR5 - 0xE000 Table 97. Open Drain Pin Mode select register 3 E414) ....... .89 (PINMODE_OD3 - address 0x4002 C074) bit Table 68.
Page 806 UM10360 NXP Semiconductors Chapter 35: Supplementary information description ......137 description ......160 Table 121.
Page 807 UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 174. Power-Down register (PowerDown - address (USBEpIntEn - address 0x5000 C234) bit 0x5000 0FF4) bit description ... . .172 description ......229 Table 175.
Page 808 UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 229. USB EP DMA Disable register (USBEpDMADis - Table 259. OTG Status Control register (OTGStCtrl - address address 0x5000 C28C) bit description..239 0x5000 C110) bit Table 230. USB DMA Interrupt Status register description .
Page 809 UM10360 NXP Semiconductors Chapter 35: Supplementary information 0x4009 C01C) bit description ... . .309 (U1RS485ADRMATCH - address 0x4001 0050) Table 282: UARTn Auto-baud Control Register (U0ACR - bit description......340 address 0x4000 C020, U2ACR - 0x4009 8020, Table 310.
Page 810 UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 333. CAN Transmit Data register A (CAN1TDA[1/2/3] - 0x4002 0004) bit description ... . . 409 address 0x4004 40[38/48/58], CAN2TDA[1/2/3] - Table 363: SPI Data Register (S0SPDR - address address 0x4004 80[38/48/58]) bit description.370...
Page 811 UM10360 NXP Semiconductors Chapter 35: Supplementary information description ......443 0x400A 800C) bit description... . . 479 Table 386.
Page 812 UM10360 NXP Semiconductors Chapter 35: Supplementary information (STCTRL - 0xE000 E010) bit description . . .506 description ......532 Table 440.
Page 813 UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 497: QEI Velocity Capture register (QEICAP - address description ......574 0x400B C034) bit description .
Page 814 UM10360 NXP Semiconductors Chapter 35: Supplementary information (DMACCxSrcAddr - 0x5000 41x0) ..602 Table 603. FMSW1 register bit description (FMSW1, Table 561. DMA Channel Destination Address registers address: 0x4008 4030) ....640 (DMACCxDestAddr - 0x5000 41x4) .
Page 815 UM10360 NXP Semiconductors Chapter 35: Supplementary information Table 650. IABR bit assignments....764 Table 651. IPR bit assignments ....765 Table 652.
Page 816: Figures
UM10360 NXP Semiconductors Chapter 35: Supplementary information 35.4 Figures Fig 1. LPC1768 simplified block diagram... . .9 Fig 50. Auto-baud a) mode 0 and b) mode 1 waveform 335 Fig 2.
Page 817 UM10360 NXP Semiconductors Chapter 35: Supplementary information Fig 88. Format of Slave Receiver mode ... .434 POLA = 0......540 Fig 89.
Page 818: Table Of Contents
UM10360 NXP Semiconductors Chapter 35: Supplementary information 35.5 Contents Chapter 1: LPC176x/5x Introductory information Introduction ......4 ARM Cortex-M3 processor .
Page 819 UM10360 NXP Semiconductors Chapter 35: Supplementary information Example 2......45 4.7.3 Peripheral Clock Selection registers 0 and 1 Example 3.
Page 820 UM10360 NXP Semiconductors Chapter 35: Supplementary information 6.5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 6.5.18 Interrupt Priority Register 7 (IPR7 - 0xE000 E40C) ....... 89 E41C).
Page 821 UM10360 NXP Semiconductors Chapter 35: Supplementary information 9.5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to 9.5.6.6 GPIO Interrupt Status for port 0 Rising Edge FIO4PIN- 0x2009 C014 to 0x2009 C094) . . 128 Interrupt (IO0IntStatR - 0x4002 8084) ..136 9.5.5...
Page 822 UM10360 NXP Semiconductors Chapter 35: Supplementary information 10.12.7 Receive Consume Index Register 10.14.3 Interrupt Clear Register (IntClear - 0x5000 (RxConsumeIndex - 0x5000 0118) ..161 0FE8) ......170 10.12.8...
Page 823 UM10360 NXP Semiconductors Chapter 35: Supplementary information 11.9.1 Power requirements ....219 11.10.5.4 USB Transmit Packet Length register 11.9.2 Clocks......219 (USBTxPLen - 0x5000 C224) .
Page 824 UM10360 NXP Semiconductors Chapter 35: Supplementary information 11.12 Serial interface engine command 11.15.4.4 Isochronous_endpoint ....259 description ......245 11.15.4.5 Max_packet_size .
Page 825 UM10360 NXP Semiconductors Chapter 35: Supplementary information 12.4.2 Software interface..... 272 12.4.2.2 USB Host Register Definitions ... 273 12.4.2.1...
Page 826 UM10360 NXP Semiconductors Chapter 35: Supplementary information 14.4.6 UARTn FIFO Control Register (U0FCR - 14.4.10.1 Auto-baud ......310 0x4000 C008, U2FCR - 0x4009 8008, U3FCR - 14.4.10.2 Auto-baud modes.
Page 827 UM10360 NXP Semiconductors Chapter 35: Supplementary information 15.5 Architecture ......342 Chapter 16: LPC176x/5x CAN1/2 16.1...
Page 828 UM10360 NXP Semiconductors Chapter 35: Supplementary information 16.14.2 Section configuration registers ... 378 16.16.3 Set and clear mechanism of the FullCAN 16.14.3 Standard Frame Individual Start Address register interrupt ......389 (SFF_sa - 0x4003 C004) .
Page 829 UM10360 NXP Semiconductors Chapter 35: Supplementary information 17.7.7 SPI Interrupt Register (S0SPINT - 0x4002 17.8 Architecture ......412 001C) .
Page 830 UM10360 NXP Semiconductors Chapter 35: Supplementary information 19.8.5 C Monitor mode control register (I2MMCTRL: 19.9.7.4 C-bus obstructed by a LOW level on SCL or C0, I2C0MMCTRL - 0x4001 C01C; I SDA ....... 464 I2C1MMCTRL- 0x4005 C01C;...
Page 831 UM10360 NXP Semiconductors Chapter 35: Supplementary information 20.5 Register description ....477 20.5.9 Transmit Clock Rate register (I2STXRATE - 0x400A 8020)......480 20.5.1...
Page 832 UM10360 NXP Semiconductors Chapter 35: Supplementary information 23.3 Description ......505 23.5.3 System Timer Current value register (STCURR - 0xE000 E018) .
Page 833 UM10360 NXP Semiconductors Chapter 35: Supplementary information 25.7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 25.7.10.2 MCPWM Capture clear address (MCCAP_CLR - 0x400B 8024, 0x400B 8028, 0x400B 802C) 534 0x400B 8074)......537 25.7.6.1...
Page 834 UM10360 NXP Semiconductors Chapter 35: Supplementary information Chapter 27: LPC176x/5x Real-Time Clock (RTC) and backup registers 27.1 Basic configuration ....559 27.6.3.1...
Page 835 UM10360 NXP Semiconductors Chapter 35: Supplementary information 30.3 Pin description ......583 30.4.3 D/A Converter Counter Value register (DACCNTVAL - 0x4008 C008).
Page 836 UM10360 NXP Semiconductors Chapter 35: Supplementary information 31.6.2.1 Peripheral-to-memory or memory-to-peripheral 31.6.4.1 Word-aligned transfers across a boundary . 612 DMA flow ......610 31.6.5...
Page 837 UM10360 NXP Semiconductors Chapter 35: Supplementary information 33.7 JTAG TAP Identification ....645 Chapter 34: Appendix: Cortex-M3 user guide 34.1 ARM Cortex-M3 User Guide: Introduction. . 646 34.2.4.2.5 Examples .
Page 838 UM10360 NXP Semiconductors Chapter 35: Supplementary information 34.2.5.1.3 Restrictions......679 34.2.5.9.4 Condition flags ..... . . 692 Note .
Page 839 UM10360 NXP Semiconductors Chapter 35: Supplementary information 34.2.9.1.3 Restrictions......708 34.2.10.6.3 Restrictions ......721 34.2.9.1.4 Condition flags .
Page 840 UM10360 NXP Semiconductors Chapter 35: Supplementary information 34.3.1.6 The Cortex Microcontroller Software Interface 34.4.2.5 Interrupt Clear-pending Registers ..763 Standard ......736 34.4.2.6...
Page 841 UM10360 NXP Semiconductors Chapter 35: Supplementary information 34.4.5.6 MPU access permission attributes ..793 34.4.5.8.2 Updating an MPU region using multi-word 34.4.5.7 MPU mismatch ..... . . 794 writes .

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