NXP Semiconductors P89LPC952 User Manual
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NXP Semiconductors P89LPC952 User Manual

NXP Semiconductors P89LPC952 User Manual

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UM10147
P89LPC952/954 User manual
Rev. 02 — 28 April 2008
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Content
Keywords
P89LPC952, P89LPC954
Abstract
Technical information for the P89LPC952/954 devices.
User manual

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Summary of Contents for NXP Semiconductors P89LPC952

  • Page 1 UM10147 P89LPC952/954 User manual Rev. 02 — 28 April 2008 User manual Document information Info Content Keywords P89LPC952, P89LPC954 Abstract Technical information for the P89LPC952/954 devices.
  • Page 2 UM10147 NXP Semiconductors P89LPC952/954 User manual Revision history Date Description 20080428 Added LQFP48 package information 20070917 Initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10147_2 © NXP B.V. 2008. All rights reserved.

  • Page 3: Introduction

    UM10147 NXP Semiconductors P89LPC952/954 User manual 1. Introduction 1.1 Pin configuration P1.3/INT0/SDA P0.4/CIN1A/KBI4/AD03 P1.2/T0/SCL P0.5/CMPREF/KBI5 P1.1/RXD0 P0.6/CMP1/KBI6 P1.0/TXD0 P3.1/XTAL1 P0.7/T1/KBI7 P89LPC952FA P3.0/XTAL2/CLKOUT P2.2/MOSI P89LPC954FA P2.3/MISO P5.7 P2.4/SS P5.6 P2.5/SPICLK P5.5 P4.0 P5.4 P4.1/TRIG 002aab307 Fig 1. PLCC44 pin configuration UM10147_2 ©...
  • Page 4 UM10147 NXP Semiconductors P89LPC952/954 User manual P1.3/INT0/SDA P0.4/CIN1A/KBI4/AD03 P1.2/T0/SCL P0.5/CMPREF/KBI5 P1.1/RXD0 P0.6/CMP1/KBI6 P1.0/TXD0 P3.1/XTAL1 P0.7/T1/KBI7 P89LPC952FBD P3.0/XTAL2/CLKOUT P2.2/MOSI P89LPC954FBD P2.3/MISO P5.7 P2.4/SS P5.6 P2.5/SPICLK P5.5 P4.0 P5.4 P4.1/TRIG 002aab306 Fig 2. LQFP44 pin configuration UM10147_2 © NXP B.V. 2008. All rights reserved.

  • Page 5: Pin Description

    UM10147 NXP Semiconductors P89LPC952/954 User manual P1.3/INT0/SDA P0.4/CIN1A/KBI4/AD03 P1.2/T0/SCL P0.5/CMPREF/KBI5 P1.1/RXD0 P0.6/CMP1/KBI6 P1.0/TXD0 VREFP P2.7 P3.1/XTAL1 P0.7/T1/KBI7 P89LPC954FBD48 P3.0/XTAL2/CLKOUT P2.2/MOSI P2.3/MISO P5.7 P2.4/SS P5.6 P2.5/SPICLK P5.5 P2.6 P5.4 P4.0 002aad095 Fig 3. LQFP48 pin configuration 1.2 Pin description Table 1.
  • Page 6 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 1. Pin description …continued Symbol Type Description LQFP48 PLCC44 LQFP44 P0.1/CIN2B/ P0.1 — Port 0 bit 1. KBI1/AD00 CIN2B — Comparator 2 positive input B. KBI1 — Keyboard input 1. AD00 — ADC0 channel 0 analog input.
  • Page 7 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 1. Pin description …continued Symbol Type Description LQFP48 PLCC44 LQFP44 P1.2/T0/SCL P1.2 — Port 1 bit 2 (open-drain when used as output). T0 — Timer/counter 0 external count input or overflow output (open-drain when used as output).
  • Page 8 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 1. Pin description …continued Symbol Type Description LQFP48 PLCC44 LQFP44 P2.2/MOSI P2.2 — Port 2 bit 2. MOSI — SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input.
  • Page 9 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 1. Pin description …continued Symbol Type Description LQFP48 PLCC44 LQFP44 P4.0 P4.0 — Port 4 bit 0. P4.1/TRIG P4.1 — Port 4 bit 1. TRIG — Debugger trigger output. P4.2/TXD1 P4.2 — Port 4 bit 2.
  • Page 10 UM10147 NXP Semiconductors P89LPC952/954 User manual P89LPC952/954 ACCELERATED 2-CLOCK 80C51 CPU TXD0 8 kB/16 kB UART0 RXD0 CODE FLASH internal 256-BYTE TXD1 UART1 DATA RAM RXD1 256-BYTE C-BUS AUXILIARY RAM AD00 AD01 PORT 5 AD02 P5[7:0] CONFIGURABLE I/Os AD03 ADC0...

  • Page 11: Special Function Registers

    UM10147 NXP Semiconductors P89LPC952/954 User manual 1.3 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
  • Page 12 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value addr.
  • Page 13 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value...
  • Page 14 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value...
  • Page 15 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value...
  • Page 16 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value...
  • Page 17 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value...
  • Page 18 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 3. Extended special function registers Name Description Bit functions and addresses Reset value addr.
  • Page 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 3. Extended special function registers …continued Name Description Bit functions and addresses Reset value addr.

  • Page 20: Memory Organization

    The P89LPC952/954 has 256 bytes of on-chip XDATA memory. CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC952/954 has 8 kB/ 16 kB of on-chip Code memory. Table 4. Data RAM arrangement...
  • Page 21 The P89LPC952/954 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC952/954 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many...

  • Page 22: Clocks

    2. Clocks 2.1 Enhanced CPU The P89LPC952/954 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

  • Page 23: Clock Output

    TRIM register. 2.4 On-chip RC oscillator option The P89LPC952 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. (Note: the initial value is better than 1 %;...

  • Page 24: Watchdog Oscillator Option

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 6. On-chip RC oscillator trim register (TRIM - address 96h) bit description Symbol Description TRIM.0 Trim value. Determines the frequency of the internal RC oscillator. During reset, these bits are loaded with a stored factory calibration value. When writing to either TRIM.1...

  • Page 25: Oscillator Clock (Oscclk) Wake-Up Delay

    Block diagram of oscillator control. 2.7 Oscillator Clock (OSCCLK) wake-up delay The P89LPC952/954 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections, the delay is 992 OSCCLK cycles plus 60 μs to 100 μs.

  • Page 26: Cpu Clock (Cclk) Modification: Divm Register

    2.9 Low power select The P89LPC952/954 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further.

  • Page 27: A/D Operating Modes

    UM10147 NXP Semiconductors P89LPC952/954 User manual • Three conversion start modes – Timer triggered start – Start immediately – Edge triggered 10-bit conversion time of 4 μs at an A/D clock of 9 MHz • • Interrupt or polled operation •...

  • Page 28: Auto Scan, Single Conversion Mode

    UM10147 NXP Semiconductors P89LPC952/954 User manual conversions. Additional conversion results will again cycle through the result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the SCC0 bit in the ADMODA register.

  • Page 29: Single Step Mode

    UM10147 NXP Semiconductors P89LPC952/954 User manual second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The first channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L, etc.

  • Page 30: Conversion Start Modes

    UM10147 NXP Semiconductors P89LPC952/954 User manual 3.2.3 Conversion start modes 3.2.3.1 Timer triggered start An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A/D operating modes.This mode is selected by the...

  • Page 31: I/O Pins Used With Adc Functions

    3V tolerant if the corresponding A/D is enabled and the device is not in power down. Otherwise the pin will remain 5V tolerant. Please refer to the P89LPC952/954 data sheet for specifications. 3.2.8 Power-down and Idle mode In Idle mode the A/D converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.
  • Page 32 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 13. A/D Mode register A (ADMODA - address 0C0h) bit allocation Symbol BNDI0 BURST0 SCC0 SCAN0 Reset Table 14. A/D Mode register A (ADMODA - address 0C0h) bit description Symbol Description Reserved. SCAN0 When = 1, selects single conversion mode (auto scan or fixed channel).

  • Page 33: Interrupts

    This bit is cleared in software by writing a 1 to this bit. 4. Interrupts The P89LPC952/954 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC952/954’s 15 interrupt sources.

  • Page 34: Interrupt Priority Structure

    IPx and IPxH (x = 0, 1) and can therefore be assigned to one of four levels, as shown in Table The P89LPC952/954 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

  • Page 35: External Interrupt Pin Glitch Suppression

    If an external interrupt has been programmed as level-triggered and is enabled when the P89LPC952/954 is put into Power-down mode or Idle mode, the interrupt occurrence will cause the processor to wake-up and resume operation. Refer to Section 6.3 “Power...

  • Page 36: I/O Ports

    5. I/O ports The P89LPC952/954 has four I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5. Ports 0, 1, 4 and 5 are 8-bit ports, Port 2 is a 6-bit port, and Port 3 is a 2-bit port. The exact...

  • Page 37: Port Configurations

    External RST pin supported Required for a clock frequency above 12 MHz. 5.1 Port configurations All but three I/O port pins on the P89LPC952/954 may be configured by software to one of four types on a pin-by-pin basis, as shown in Table 24.

  • Page 38: Open Drain Output Configuration

    The quasi-bidirectional port configuration is shown in Figure Although the P89LPC952/954 is a 3 V device most of the pins are 5 V-tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V causing extra power consumption.

  • Page 39: Input-Only Configuration

    5.4 Input-only configuration The input port configuration is shown in Figure 12. It is a Schmitt-triggered input that also has a glitch suppression circuit. (Please refer to the P89LPC952/954 data sheet, Dynamic characteristics for glitch filter specifications). input port data...

  • Page 40: Port 0 And Analog Comparator Functions

    Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open drain. Every output on the P89LPC952/954 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded.
  • Page 41 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 25. Port output configuration Port pin Configuration SFR bits PxM1.y PxM2.y Alternate usage Notes P0.0 P0M1.0 P0M2.0 KBIO, CMP2, AD05 P0.1 P0M1.1 P0M2.1 KBI1, CIN2B, AD00 Refer to Section 5.6 “Port 0 and Analog Comparator functions”...

  • Page 42: Power Monitoring Functions

    Brownout trip voltage, VBO (see P89LPC952/954 data sheet, Static characteristics), and is negated when V rises above VBO. If the P89LPC952/954 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent...

  • Page 43: Power-On Detection

    0 to the bit. Note that if BOE (UCFG1.5) is programmed, BOF (RSTSRC.5) will be set when POF is set. If BOE is unprogrammed, BOF is meaningless. 6.3 Power reduction modes The P89LPC952/954 supports three different power reduction modes as determined by SFR bits PCON[1:0] (see Table 27).
  • Page 44 Power-down mode: The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC952/954 exits Power-down mode via any reset, or certain interrupts - external pins INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, and comparator trips. Waking up by reset is only enabled if the corresponding reset is enabled, and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit (IEN0.7) is set.
  • Page 45 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 28. Power Control register (PCON - address 87h) bit allocation Symbol SMOD1 SMOD0 BOPD PMOD1 PMOD0 Reset Table 29. Power Control register (PCON - address 87h) bit description Symbol Description PMOD0 Power Reduction Mode (see Section 6.3)

  • Page 46: Reset

    Note: During a power cycle, V must fall below V (see P89LPC952/954 data sheet, Static characteristics) before power is reapplied, in order to ensure a power-on reset. Note: When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled.
  • Page 47 UM10147 NXP Semiconductors P89LPC952/954 User manual For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit may be set: •...

  • Page 48: Reset Vector

    P89LPC952/954 User manual 7.1 Reset vector Following reset, the P89LPC952/954 will fetch instructions from either address 0000h or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address = 00h. The Boot address will be used if a UART break reset occurs or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the...

  • Page 49: Mode 0

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 36. Timer/Counter Mode register (TMOD - address 89h) bit description …continued Bit Symbol Description T1M0 Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the...

  • Page 50: Mode 1

    Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P89LPC952/954 device can look like it has three Timer/Counters. Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3.
  • Page 51 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 39. Timer/Counter Control register (TCON) - address 88h) bit allocation Symbol Reset Table 40. Timer/Counter Control register (TCON - address 88h) bit description Bit Symbol Description Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

  • Page 52: Timer Overflow Toggle Output

    UM10147 NXP Semiconductors P89LPC952/954 User manual C/T = 0 overflow PCLK interrupt Tn pin (8-bits) control C/T = 1 reload toggle Tn pin Gate (8-bits) INTn pin ENTn 002aaa921 Fig 17. Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload).

  • Page 53: Real-Time Clock System Timer

    PCLK as the clock source for the timer. 9. Real-time clock system timer The P89LPC952/954 has a simple Real-time Clock/System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down. The...

  • Page 54: Real-Time Clock Source

    UM10147 NXP Semiconductors P89LPC952/954 User manual 9.1 Real-time clock source RTCS1/RTCS0 (RTCCON[6:5]) are used to select the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CPU clock. If the internal crystal oscillator or the external clock input on XTAL1 is used as the CPU clock, then the RTC will use CCLK as its clock source.
  • Page 55 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 41. Real-time Clock/System Timer clock sources …continued FOSC2:0 RCCLK RTCS1:0 RTC clock source CPU clock source Low frequency crystal Low frequency crystal /DIVM Low frequency crystal /DIV Low frequency crystal Internal RC oscillator...

  • Page 56: Uarts

    0. It can be cleared in software. 10. UARTs The P89LPC952/954 has two enhanced UARTs that are compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC952/954 does include an independent Baud Rate Generator for each UART.

  • Page 57: Mode 3

    FFB3H 10.6 Baud Rate generator and selection The P89LPC952/954 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a value programmed into the BRGR1_n and BRGR0_n SFRs. Each UART can use either Timer 1 or the baud rate generator output as determined by...

  • Page 58: Updating The Brgr1 And Brgr0 Sfrs

    UM10147 NXP Semiconductors P89LPC952/954 User manual 10.7 Updating the BRGR1 and BRGR0 SFRs The baud rate SFRs, BRGR1_n and BRGR0_n must only be loaded when the Baud Rate Generator is disabled (the BRGEN_0 bit in the BRGCON_n register is logic 0). This avoids the loading of an interim value to the baud rate generator.

  • Page 59: Framing Error

    UM10147 NXP Semiconductors P89LPC952/954 User manual timer 1 overflow SMOD1 = 1 (PCLK-based) SBRGS = 0 ÷2 baud rate modes 1 and 3 SMOD1 = 0 SBRGS = 1 baud rate generator 002aaa897 (CCLK-based) Fig 21. Baud rate generation for UARTs (Modes 1, 3).
  • Page 60 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 51. Serial Port 0 Control register (S0CON - address 98h) bit description …continued Bit Symbol Description SM2_0 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0.
  • Page 61 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 54. Serial Port modes SM0_n, SM1_n UART mode UART baud rate ⁄ CCLK Mode 0: shift register (default mode on any reset) Mode 1: 8-bit UART Variable (see Table ⁄ ⁄ CCLK CCLK...

  • Page 62: More About Uart Mode 0

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 57. Serial Port 1 Status register (S1STAT - address D4h) bit allocation Symbol DBMOD INTLO_1 CIDIS_1 DBISEL_ FE_1 BR_1 OE_1 STINT_1 Reset Table 58. Serial Port 1 Status register (S1STAT - address D4h) bit description...

  • Page 63: More About Uart Mode 1

    UM10147 NXP Semiconductors P89LPC952/954 User manual Reception is initiated by clearing RI_n (SnCON.0). Synchronous serial transfer occurs and RI_n will be set again at the end of the transfer. When RI_n is cleared, the reception of the next character will begin. Refer to Figure 22 S1 ...

  • Page 64: More About Uart Modes 2 And 3

    UM10147 NXP Semiconductors P89LPC952/954 User manual TX clock write to SBUF transmit shift start stop bit INTLO = 0 INTLO = 1 clock start ÷16 reset stop bit receive shift 002aaa926 Fig 23. Serial Port Mode 1 (only single transmit buffering case is shown).

  • Page 65: Break Detect

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 59. FE_n and RI_n when SM2_n = 1 in Modes 2 and 3 Mode PCON.6 RB8_n RI_n FE_n (SMOD0) No RI_n when RB8_n = 0 Occurs during STOP Similar to Figure 24, with SMOD0 = 0, R_n Occurs during STOP...

  • Page 66: The 9Th Bit (Bit 8) In Double Buffering (Modes 1, 2, And 3)

    UM10147 NXP Semiconductors P89LPC952/954 User manual – If DBISEL_n is logic 1 and INTLO_n is logic 0, a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter (which is also the last data).

  • Page 67: Multiprocessor Communications

    UM10147 NXP Semiconductors P89LPC952/954 User manual If double buffering is enabled, TB8_n MUST be updated before SnBUF is written, as TB8_n will be double-buffered together with SnBUF data. The operation described in the Section 10.17 “Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)” on...

  • Page 68: Automatic Address Recognition

    UM10147 NXP Semiconductors P89LPC952/954 User manual Note that SM2_n has no effect in Mode 0, and must be logic 0 in Mode 1. 10.20 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons.

  • Page 69: C Interface

    I C-bus will not be released. The P89LPC952/954 device provides a byte-oriented I C interface. It has four operation modes: Master Transmitter Mode, Master Receiver Mode, Slave Transmitter Mode and...

  • Page 70: C Data Register

    C MCU INTERFACE INTERFACE 002aac130 Fig 26. I C-bus configuration. The P89LPC952/954 CPU interfaces with the I C-bus through six Special Function Registers (SFRs): I2CON (I C Control Register), I2DAT (I C Data Register), I2STAT (I Status Register), I2ADR (I C Slave Address Register), I2SCLH (SCL Duty Cycle Register High Byte), and I2SCLL (SCL Duty Cycle Register Low Byte).

  • Page 71: C Control Register

    UM10147 NXP Semiconductors P89LPC952/954 User manual 11.3 I C control register The CPU can read and write this register. There are two bits are affected by hardware: the SI bit and the STO bit. The SI bit is set by hardware and the STO bit is cleared by hardware.

  • Page 72: C Status Register

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 66. C Control register (I2CON - address D8h) bit description …continued Bit Symbol Description C Interrupt Flag. This bit is set when one of the 25 possible I C states is entered. When EA bit and EI2C (IEN1.0) bit are both set, an interrupt is requested when SI is set.

  • Page 73: C Operation Modes

    UM10147 NXP Semiconductors P89LPC952/954 User manual The values for I2SCLL and I2SCLH do not have to be the same; the user can give different duty cycles for SCL by setting these two registers. However, the value of the register must ensure that the data rate is in the I C data rate range of 0 to 400 kHz.

  • Page 74: Master Receiver Mode

    UM10147 NXP Semiconductors P89LPC952/954 User manual The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.

  • Page 75: Slave Receiver Mode

    UM10147 NXP Semiconductors P89LPC952/954 User manual slave address DATA DATA data transferred logic 0 = write (n Bytes + acknowledge) logic 1 = read A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) from master to slave S = START condition...

  • Page 76: Slave Transmitter Mode

    UM10147 NXP Semiconductors P89LPC952/954 User manual slave address DATA DATA P/RS logic 0 = write data transferred logic 1 = read (n Bytes + acknowledge) A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) from master to slave...
  • Page 77 UM10147 NXP Semiconductors P89LPC952/954 User manual I2ADR ADDRESS REGISTER P1.3 COMPARATOR INPUT FILTER P1.3/SDA SHIFT REGISTER OUTPUT STAGE I2DAT BIT COUNTER / ARBITRATION CCLK INPUT TIMING AND SYNC LOGIC FILTER CONTROL P1.2/SCL LOGIC SERIAL CLOCK OUTPUT interrupt GENERATOR STAGE timer 1 overflow P1.2...
  • Page 78 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 72. Master Transmitter mode Status code Status of the I Application software response Next action taken by I (I2STAT) hardware hardware to/from I2DAT to I2CON A START Load SLA+W SLA+W will be transmitted;...
  • Page 79 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 72. Master Transmitter mode …continued Status code Status of the I Application software response Next action taken by I (I2STAT) hardware hardware to/from I2DAT to I2CON Data byte in Load data byte or 0 Data byte will be transmitted;...
  • Page 80 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 73. Master Receiver mode …continued Status code Status of the I Application software response Next action taken by I C hardware (I2STAT) hardware to/from I2DAT to I2CON STA STO SI Data byte has Read data byte Data byte will be received;...
  • Page 81 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 74. Slave Receiver mode …continued Status code Status of the I Application software response Next action taken by I (I2STAT) hardware hardware to/from I2DAT to I2CON STO SI Previously Read data byte or 0...
  • Page 82 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 74. Slave Receiver mode …continued Status code Status of the I Application software response Next action taken by I (I2STAT) hardware hardware to/from I2DAT to I2CON STO SI A STOP condition No I2DAT action...

  • Page 83: Serial Peripheral Interface (Spi)

    12. Serial Peripheral Interface (SPI) The P89LPC952/954 provides another high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master or Slave mode.
  • Page 84 UM10147 NXP Semiconductors P89LPC952/954 User manual MISO P2.3 CPU clock 8-BIT SHIFT REGISTER MOSI P2.2 READ DATA BUFFER DIVIDER CONTROL BY 4, 16, 64, 128 LOGIC SPICLK P2.5 clock SPI clock (master) SELECT CLOCK LOGIC P2.4 MSTR SPEN SPI CONTROL...
  • Page 85 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 77. SPI Control register (SPCTL - address E2h) bit description Bit Symbol Description SPR0 SPI Clock Rate Select SPR1, SPR0: SPR1 ⁄ CCLK 00 — ⁄ CCLK 01 — ⁄ CCLK 10 —...
  • Page 86 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 80. SPI Data register (SPDAT - address E3h) bit allocation Symbol Reset master slave MISO MISO 8-BIT SHIFT 8-BIT SHIFT MOSI MOSI REGISTER REGISTER SPICLK SPICLK SPI CLOCK PORT GENERATOR 002aaa901 Fig 34. SPI single master single slave configuration.

  • Page 87: Configuring The Spi

    UM10147 NXP Semiconductors P89LPC952/954 User manual master slave MISO MISO 8-BIT SHIFT 8-BIT SHIFT MOSI MOSI REGISTER REGISTER SPICLK SPICLK SPI CLOCK port GENERATOR slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK port 002aaa903 Fig 36. SPI single master multiple slaves configuration.

  • Page 88: Additional Considerations For A Slave

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 81. SPI master and slave selection …continued SPEN SSIG SS Pin MSTR Master MISO MOSI SPICLK Remarks or Slave Mode Master input Hi-Z Hi-Z MOSI and SPICLK are at high-impedance to avoid bus contention when the MAster is idle.

  • Page 89: Write Collision

    UM10147 NXP Semiconductors P89LPC952/954 User manual slave and start sending data to it. To avoid bus contention, the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be an input and MISO becomes an output.
  • Page 90 UM10147 NXP Semiconductors P89LPC952/954 User manual Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) 002aaa934 (1) Not defined Fig 37.
  • Page 91 UM10147 NXP Semiconductors P89LPC952/954 User manual Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) 002aaa935 (1) Not defined Fig 38.
  • Page 92 UM10147 NXP Semiconductors P89LPC952/954 User manual Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) 002aaa936 (1) Not defined Fig 39.

  • Page 93: Spi Clock Prescaler Select

    77). 13. Analog comparators Two analog comparators are provided on the P89LPC952/954. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage).
  • Page 94 UM10147 NXP Semiconductors P89LPC952/954 User manual When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

  • Page 95: Internal Reference Voltage

    P89LPC952/954 User manual 13.2 Internal reference voltage An internal reference voltage, Vref, may supply a default reference when a single comparator input pin is used. Please refer to the P89LPC952/954 data sheet for specifications 13.3 Comparator input pins Comparator input and reference pins maybe be used as either digital I/O or as inputs to the comparator.

  • Page 96: Comparators Configuration Example

    UM10147 NXP Semiconductors P89LPC952/954 User manual CINnA CINnA CMPn CMPREF CMPREF 002aaa618 002aaa620 a. CPn, CNn, OEn = 0 0 0 b. CPn, CNn, OEn = 0 0 1 CINnA CINnA CMPn (1.23 V) (1.23 V) 002aaa621 002aaa622 c. CPn, CNn, OEn = 0 1 0 d.

  • Page 97: Keypad Interrupt (Kbi)

    UM10147 NXP Semiconductors P89LPC952/954 User manual 14. Keypad interrupt (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition.

  • Page 98: Watchdog Timer (Wdt)

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 88. Keypad Interrupt Mask register (KBMASK - address 86h) bit allocation Symbol KBMASK.7 KBMASK.6 KBMASK.5 KBMASK.4 KBMASK.3 KBMASK.2 KBMASK.1 KBMASK.0 Reset Table 89. Keypad Interrupt Mask register (KBMASK - address 86h) bit description...

  • Page 99: Feed Sequence

    UM10147 NXP Semiconductors P89LPC952/954 User manual Figure 45 shows the watchdog timer in watchdog mode. It consists of a programmable 13-bit prescaler, and an 8-bit down counter. The down counter is clocked (decremented) by a tap taken from the prescaler. The clock source for the prescaler is either PCLK or the watchdog oscillator selected by the WDCLK bit in the WDCON register.
  • Page 100 SETB EA ;enable interrupt This sequence assumes that the P89LPC952/954 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence. If an interrupt was allowed to be serviced and the service routine contained any SFR writes, it would trigger a watchdog reset.
  • Page 101 UM10147 NXP Semiconductors P89LPC952/954 User manual The maximum number of tclks is: ) 255 tclks 1048577 Table 93 shows sample P89LPC952/954 timeout values. Table 91. Watchdog Timer Control register (WDCON - address A7h) bit allocation Symbol PRE2 PRE1 PRE0 WDRUN...

  • Page 102: Watchdog Clock Source

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 93. Watchdog timeout vales …continued PRE2 to PRE0 WDL in decimal) Timeout Period Watchdog Clock Source (in watchdog clock 400 KHz Watchdog 12 MHz CCLK (6 MHz ⁄ cycles) CCLK Oscillator Clock Watchdog...

  • Page 103: Watchdog Timer In Timer Mode

    UM10147 NXP Semiconductors P89LPC952/954 User manual WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH watchdog 8-BIT DOWN oscillator ÷32 PRESCALER reset COUNTER PCLK SHADOW REGISTER PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK WDCON (A7H) 002aaa905 Fig 44. Watchdog Timer in Watchdog Mode (WDTE = 1).

  • Page 104: Power-Down Operation

    This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register. SRST Software Reset. When set by software, resets the P89LPC952/954 as if a hardware reset occurred. ENT0 When set the P1.2 pin is toggled whenever Timer 0 overflows.

  • Page 105: Software Reset

    DPTR) will be affected by the setting of DPS. The MOVX instructions have limited application for the P89LPC952/954 since the part does not have an external data bus. However, they may be used to access Flash configuration information (see Flash Configuration section) or auxiliary data (XDATA) memory.

  • Page 106: Debugger Connections

    TCLK Serial clock signal from the debugger. DBINST Debugger installed signal. Driven high by the debugger when debugger is active. I/O direction is with respect to the P89LPC952/954 target system. UM10147_2 © NXP B.V. 2008. All rights reserved. User manual Rev.

  • Page 107: Flash Memory

    20-year minimum data retention 17.3 Flash programming and erase The P89LPC952/954 program memory consists 1 kB sectors. Each sector can be further divided into 64-byte pages. In addition to sector erase and page erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.

  • Page 108: Using Flash As Data Storage: Iap-Lite

    UM10147 NXP Semiconductors P89LPC952/954 User manual • A factory-provided default serial loader, located in upper end of user program memory, providing In-System Programming (ISP) via the serial port. • Two-wire serial debugger. 17.4 Using Flash as data storage: IAP-Lite The Flash code memory array of this device supports IAP-Lite in addition to standard IAP functions.
  • Page 109 UM10147 NXP Semiconductors P89LPC952/954 User manual OI flag (FMCON.0) after each erase-programming operation to see if the operation was aborted. If the operation was aborted, the user’s code will need to repeat the process starting with loading the page register.
  • Page 110 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 100. Flash Memory Control register (FMCON - address E4h) bit description …continued Symbol Access Description High voltage abort. Set if either an interrupt or a brown-out is detected during a program or erase cycle. Also set if the brown-out detector is disabled at the start of a program or erase cycle.

  • Page 111: In-Circuit Programming (Icp)

    The In-Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC952/954 through a two-wire serial interface. NXP has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area.

  • Page 112: Isp And Iap Capabilities Of The P89Lpc952/954

    The P89LPC952/954 contains two special Flash elements: the BOOT VECTOR and the Boot Status Bit. Following reset, the P89LPC952/954 examines the contents of the Boot Status Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code.

  • Page 113: In-System Programming (Isp)

    The ISP feature requires that an initial character (an uppercase U) be sent to the P89LPC952/954 to establish the baud rate. The ISP firmware provides auto-echo of received characters. Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records.
  • Page 114 Should an error occur in the checksum, the P89LPC952/954 will send an ‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed.
  • Page 115 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 102. In-system Programming (ISP) hex record formats Record type Command/data function Program User Code Memory Page: nnaaaa00dd..ddcc Where: nn = number of bytes to program; aaaa = page address; dd..dd= data bytes; cc = checksum;...
  • Page 116 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 102. In-system Programming (ISP) hex record formats …continued Record type Command/data function Miscellaneous Read Functions: 01xxxx03sscc Where xxxx = required field but value is a ‘don’t care’; ss= subfunction code; cc = checksum...

  • Page 117: In-Application Programming (Iap)

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 102. In-system Programming (ISP) hex record formats …continued Record type Command/data function Read Global CRC: 00xxxx06cc Where: xxxx = required field but value is a ‘don’t care’; cc= checksum Example: 00000006FA Direct Load of Baud Rate: 02xxxx07HHLLcc Where: xxxx = required field but value is a ‘don’t care’;...

  • Page 118: Configuration Byte Protection

    UM10147 NXP Semiconductors P89LPC952/954 User manual The WE flag is SET by writing the Set Write Enable (08H) command to FMCON followed by a key value (96H) to FMDATA: FMCON = 0x08; FMDATA = 0x96; The WE flag is CLEARED by writing the Clear Write Enable (0BH) command to FMCON followed by a key value (96H) to FMDATA, or by a reset: FMCON = 0x0B;...
  • Page 119 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 103. IAP error status Flag Description Operation Interrupted. Indicates that an operation was aborted due to an interrupt occurring during a program or erase cycle. Security Violation. Set if program or erase operation fails due to security settings. Cycle is aborted. Memory contents are unchanged.
  • Page 120 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 104. IAP function calls IAP function IAP call parameters Program User Code Page Input parameters: (requires ‘key’) ACC = 00h R3= number of bytes to program R4= page address (MSB) R5= page address (LSB)
  • Page 121 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 104. IAP function calls …continued IAP function IAP call parameters Misc. Read Input parameters: ACC = 03h R7= register address 00= UCFG1 01= UCFG2 02= Boot Vector 03= Status Byte 04 to 07 = reserved...

  • Page 122: User Configuration Bytes

    R7= data 17.17 User configuration bytes A number of user-configurable features of the P89LPC952/954 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of an Flash byte UCFG1 shown in Table 106 Table 105.

  • Page 123: User Security Bytes

    UM10147 NXP Semiconductors P89LPC952/954 User manual Table 106. Flash User Configuration Byte 1 (UCFG1) bit description …continued Bit Symbol Description WDSE Watchdog Safety Enable bit. Refer to Table 90 “Watchdog timer configuration” for details. Brownout Detect Enable (see Section 6.1 “Brownout detection”)

  • Page 124: Boot Vector Register

    0:4 BOOTV[0:4] Boot vector. If the Boot Vector is selected as the reset address, the P89LPC952/954 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset.

  • Page 125: Boot Status Register

    Bit Symbol Description Boot Status Bit. If programmed to logic 1, the P89LPC952/954 will always start execution at an address comprised of 00H in the lower eight bits and BOOTVEC as the upper bits after a reset. (See Section 7.1 “Reset vector”...

  • Page 126: Instruction Set

    UM10147 NXP Semiconductors P89LPC952/954 User manual 18. Instruction set Table 117. Instruction set summary Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A,Rn Add register to A 28 to 2F ADD A,dir Add direct byte to A ADD A,@Ri Add indirect memory to A...
  • Page 127 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 117. Instruction set summary …continued Mnemonic Description Bytes Cycles Hex code XRL A,Rn Exclusive-OR register to A 68 to 6F XRL A,dir Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect memory to A...
  • Page 128 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 117. Instruction set summary …continued Mnemonic Description Bytes Cycles Hex code XCHD A,@Ri Exchange A and indirect memory nibble D6 to D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry...
  • Page 129 Notice: All referenced brands, product names, service names and trademarks information. are the property of their respective owners. Right to make changes — NXP Semiconductors reserves the right to make C-bus — logo is a trademark of NXP B.V. changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice.

  • Page 130: Tables

    UM10147 NXP Semiconductors P89LPC952/954 User manual 20. Tables Table 1. Pin description ......5 Table 35. Timer/Counter Mode register (TMOD - address Table 2.
  • Page 131 UM10147 NXP Semiconductors P89LPC952/954 User manual Table 66. I C Control register (I2CON - address D8h) bit Table 101.Boot loader address and default Boot vector 112 description ......71 Table 102.In-system Programming (ISP) hex record formats...

  • Page 132: Figures

    Block diagram ......10 Fig 5. P89LPC952 memory map - P89LPC954 is similar . Fig 6.

  • Page 133: Table Of Contents

    UM10147 NXP Semiconductors P89LPC952/954 User manual 22. Contents Introduction ......3 Power reduction modes ....43 Pin configuration .
  • Page 134 In-circuit programming (ICP)... . . 111 17.6 ISP and IAP capabilities of the P89LPC952/954 . 17.7 Boot ROM ......112 17.8...

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