NXP Semiconductors PN7462 series User Manual page 70

NXP Semiconductors
Bit Symbol
7.7.4 INPUT CLOCK DETECTOR CONTROL REGISTER
Table 64. CLKGEN_INPUT_CLOCK_DETECTOR_CONTROL_REG (address 0024h)
Bit Symbol
31:14 RESERVED
14 USB_PLL_CLK_IN_OK_BYPASS
13 USB_CLK_DETECT_ENABLE
12:5 INPUT_USB_CLOCK_EDGES_NUM
BER
4:0 DETECTION_WINDOW_LENGTH
7.7.5 CLOCK PRESENCE BYPASS REG
Table 65. CLKGEN_CLOCK_PRESENCE_BYPASS_REG (address 002Ch)
Bit Symbol
31:2 RESERVED
1 CLOCK_PRESENCE_BYPASS_V
AL
0 CLOCK_PRESENCE_BYPASS_E
NABLE
UM10858
User manual
COMPANY PUBLIC
Access Value Description
0: Disable the CLIF PLL
Access Value
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x80
R/W 0x0D
Access Value Description
R/W 0x0 Reserved
R/W 0x0 Value to apply to clif_pll_lock2_o signal when
corresponding enable bit is set
0: set clif_pll_lock2_o signal to 0
1: set clif_pll_lock2_o signal to 1
R/W 0x0 1: Enable bypass of the clif_pll_lock2_o signal to the
value stored in clock_presence_bypass_val
0: Disable Bypass of the clif_pll_lock2_o signal
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Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
Reserved
usb pll clk_in detection override
1: usb_pll_clk_in detection overridden. Clk_in_ok
set to '1'
Enable usb_pll_clk_in detect
1: Enable usb_pll_clk_in detection
Defines the expected amount of input clock edges
during the detection window length. Default value is
set to detect a 27.12 MHz input clock.
Defines the detection window length (in HFO/8
clock cycles).
Default value is set to detect a 27.12 MHz input
clock.
UM10858
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