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NXP Semiconductors
Bit
5
4
3:0
[1]
HOSTIF_INT_SET_ENABLE_REG
This register is a collection of set interrupt enable commands. Writing 1 to this register
does set the corresponding interrupt request enable flag. Writing 0 to this register has no
effect.
Table 349. HOSTIF_INT_SET_ENABLE_REG (address offset 0x3FDC)
Bit
31:27
26
25
24
23
22
UM10858
User manual
COMPANY PUBLIC
Symbol
RX_BUFFER_NOT_A
VAILABLE_CLR_ENA
BLE
EOT_CLR_ENABLE
EOR_CLR_ENABLE
An interrupt event which has its clear enable bit set simply means that the external interrupt is not
asserted. However, the event itself is still triggered. Thus, even if the CPU is using a polling mechanism
instead of being interrupt-driven, the firmware must still ensure that the event is cleared by setting the
associated bit in register HOSTIF_INT_CLR_STATUS_REG.
Symbol
RESERVED
HSU_RX_FER_SET_E
NABLE
BUFFER_CFG_CHAN
GED_ERROR_SET_E
NABLE
AHB_WR_SLOW_SET
_ENABLE
AHB_RD_SLOW_SET
_ENABLE
AHB_ERROR_SET_E
NABLE
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Access
Reset
Description
Value
W
0
1 - clear enable for no receive buffers
available interrupt
0 - no effect
W
0
1 - clear enable for EOT interrupt
0 - no effect
W
0
1 - clear enable for End of Reception
(EOR) in buffer N (0<=N<=3) interrupt
0001 - clear enable for EOR interrupt for
RX buffer 0
0010 - clear enable for EOR interrupt for
RX buffer 1
0100 - clear enable for EOR interrupt for
RX buffer 2
1000 - clear enable for EOR interrupt for
RX buffer 3
0000 - no effect
Access
Reset
Description
Value
W
0
Reserved
W
0
1 - set enable for HSU RX frame error
interrupt0 - no effect
W
0
1 - set enable for buffer configuration
changed during use interrupt
0 - no effect
W
0
1 - set enable for slow AHB during write
operation interrupt
0 - no effect
1 - set enable for slow AHB during read
W
0
operation interrupt
0 - no effect
W
0
1 - set enable for ahb_error (hresp=1,
oraddress overflow) interrupt
0 - no effect
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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