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19. List of tables
Table 1.
Ordering information ......................................... 7
Table 2.
Wait states for write access on EEPROM ....... 17
Table 3.
Wait states for read access on EEPROM ....... 18
Table 4.
Wait states for write access on EEPROM ....... 18
Table 5.
Wait states for read access on EEPROM ....... 19
Table 6.
Clock generator register overview ................... 19
Table 7.
EE_CTRL (address offset 0x0000h) ............... 20
Table 8.
EE_DYN (address offset 0x0004h) ................. 20
Table 9.
EE_STAT_DAT (address offset 0x0008h) ...... 21
Table 10. EE_STAT_COD (address offset 0x000Ch) ..... 22
Table 11. EE_CRC_DAT (address offset 0x0010h) ........ 22
Table 12. EE_CRC_DAT_ADDR (address offset 0x0014h)
........................................................................ 22
Table 13. EE_CRC_1_COD_INIT (address offset
0x0018h) ......................................................... 23
Table 14. EE_CRC_1_COD (address offset 0x001Ch) .. 23
Table 15. EE_CRC_1_COD_ADDR (address offset
0x0020h) ......................................................... 23
Table 16. EE_CRC_0_COD_INIT (address offset
0x0024h) ......................................................... 23
Table 17. EE_CRC_0_COD (address offset 0x0028h) ... 23
Table 18. EE_CRC_0_COD_ADDR (address offset
0x002Ch) ........................................................ 24
Table 19. EE_CRC_0_COD_ADDR (address offset
0x002Ch) ........................................................ 24
Table 20. EE_TRIMM (address offset 0x003Ch) ............ 24
Table 21. EE_ECC_PF_AHB_ERROR_ADDR (address
offset 0x0044h) ............................................... 24
Table 22. EE_INT_CLR_ENABLE (address offset
0x0FD8h) ........................................................ 24
Table 23. EE_INT_SET_ENABLE (address offset
0x0FDCh)........................................................ 25
Table 24. EE_INT_STATUS (address offset 0x0FE0h) .. 25
Table 25. EE_INT_ENABLE (address offset 0x0FE4h) .. 26
Table 26. EE_INT_CLR_STATUS (address offset
0x0FE8h) ........................................................ 27
Table 27. EE_INT_SET_STATUS (address offset
0x0FECh) ........................................................ 27
Table 28. External interrupt sources ............................... 28
Table 29. NVIC register overview ................................... 30
Table 30. NVIC_IPRn bit assignments............................ 30
Table 31. SWD pinning ................................................... 31
Table 32. SysTick timer (base address 0xE000 E000) ... 31
Table 33. Voltage and Supply pins connection overview 38
Table 34. Start-up times of LDOs ................................... 42
UM10858
User manual
COMPANY PUBLIC
Table 35. Voltage monitor - possible threshold
Table 36. Latency of voltage monitors ............................ 45
Table 37. PMU register overview (base address 0x4000
Table 38. PMU_STATUS_REG (address offset 0x0000) 46
Table 39. PMU_BG_MON_CONTROL_REG (address
Table 40. PMU_TXLDO_CONTROL_REG (address offset
Table 41. PMU_LDO_CONTROL_REG (address offset
Table 42. PMU_INTERRUPT_CLR_ENABLE_REG
Table 43. PMU_INTERRUPT_SET_ENABLE_REG
Table 44. PMU_INTERRUPT_STATUS_REG (address
Table 45. PMU_INTERRUPT_ENABLE_REG (address
Table 46. PMU_INTERRUPT_CLR_STATUS_REG
Table 47. PMU_INTERRUPT_SET_STATUS_REG
Table 48. TXLDO Register .............................................. 54
Table 49. Crystal requirements ....................................... 56
Table 50. Optimum divider settings for PLL1 and PLL2 .. 61
Table 51. Clock generator register overview (base
Table 52. CLKGEN_STATUS_REG (address 0000h) ..... 62
Table 53. Oscillators Registers ....................................... 63
Table 54. CLKGEN_HFO_XTAL_REG (address 0004h) 63
Table 55. CLKGEN_HFO_TRIMM_REG (address 0008h)
Table 56. USB PLL Registers ......................................... 64
Table 57. CLKGEN_USB_PLL_CONTROL_REG (address
Table 58.
Table 59.
Table 60. CLIF PLL register overview ............................. 67
Table 61. CLKGEN_CLIF_PLL1_CONTROL_REG
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
configuration .................................................... 43
8000) ............................................................... 45
offset 0x0004) ................................................. 47
0x0008) ........................................................... 47
0x000C)........................................................... 49
(address offset 0x3FD8) .................................. 50
(address offset 0x3FDC) ................................. 50
offset 0x3FE0) ................................................. 51
offset 0x3FE4) ................................................. 52
(address offset 0x3FE8) .................................. 52
(address offset 0x3FEC) ................................. 53
address 0x4001 0000)..................................... 61
........................................................................ 64
000Ch) ............................................................ 65
CLKGEN_USB_PLL_MDEC_WO_SOFTDEC_R
EG (address 0010h) ........................................ 66
CLKGEN_USB_PLL_NDEC_PDEC_WO_SOFT
DEC_REG (address 0014h) ............................ 67
(address 0018h) .............................................. 68
© NXP B.V. 2018. All rights reserved.
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