NXP Semiconductors PN7462 series User Manual page 215

NXP Semiconductors
13.6.2 Registers description
13.6.2.1 Register ct_ssr_reg (Slot Select Register)
This configuration register enables to select the I/O line used and also to reset the whole
Contact UART.
Table 249. Ct_ssr_reg (address 0000h) bit description
Bit Symbol Access
31:5 RESERVED -
4 pres_con_no R/W
3 pres_pup_en R/W
2 CLKAUXen R/W
1 IOAUXen R/W
0 softreset R/W
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Reset Description
Value
0 Reserved
0 PRESN CONnector Normally Open
When set to logic 0, the type of connector used for card detection is normally
closed.
When set to logic 1, the type of connector used for card detection is normally
open.
In conjunction with pres_pup_en bit, this enables to support the two types of
connector (normally open and normally closed) for card detection.
Remark: this bit has to be set to the value corresponding to the connector used
before any activation.
0 PRESN internal Pull UP ENable
When set to logic 0, an internal pull-down resistance is connected to PRESN
pin for card detection.
When set to logic 1, an internal pull up resistance is connected to PRESN pin
for card detection.
In conjunction with pres_con_no bit, this enables to support the two types of
connector (normally open and normally closed) for card detection.
Remark: this bit has to be set to the value corresponding to the connector used
before any activation.
0 CLK AUXiliary enable
When set to logic 1, outputs CLKAUX clock on CLKAUX pin. This can be used
also to perform clock stop; CST bit is therefore not available for the auxiliary
slot in ct_ccr2_reg register.
0 I/O AUXiliary enable
Select the second (auxiliary) slot.
Note: Changing the value of this bit (switching from one slot to the other one)
resets the ISO UART block, the interrupt bits ft, fer, ovr, pe, EARLY, MUTE
(ct_usr1_reg register), wrdaccerr, to1, to2 and to3 (ct_usr2_reg register), the
Timers block and ct_toc_reg register.
1 When set to logic 0 this bit resets the whole Contact UART (software reset),
sets to logic 1 automatically by hardware after after one clock cycle if slot 1 is
not activated else after one clock cycle after slot 1 has been automatically
deactivated. Software should check soft reset is finished by reading ct_ssr_reg
register before any further action.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
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