NXP Semiconductors PN7462 series User Manual page 330

NXP Semiconductors
15.4.2.10 USB Interrupt enable register
Table 365. USB Interrupt enable register (address offset = 0x24)
Reset value: 0x00000000
Bit Symbol
31:0 INT_EN
15.4.2.11 USB set interrupt status register
Table 366. USB set interrupt status register (address offset = 0x28)
Reset value: 0x00000000
Bit Symbol
31:0 SET_EN
15.4.2.12 USB interrupt routing register
Table 367. USB interrupt routing register (address offset = 0x2C)
Reset value: 0x00000000
Bit Symbol
31:0 ROUTE_INT
15.4.2.13 USB configuration
Table 368. USB configuration (address offset = 0x30)
Reset value: see configuration values
Bit Symbol
4:0 PHYSEP
5 SB
6 DB
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Value Description
If this bit is set and the corresponding USB interrupt status bit is set
a hardware interrupt is generated on the interrupt line indicated by
the corresponding USB interrupt routing bit.
Value Description
If firmware writes a one to one of these bits, the corresponding USB
interrupt status bit is set. When this register is read, the same value
as the USB interrupt status register is returned.
Value Description
This bit can control on which hardware interrupt line the
interrupt will be generated:
0 IRQ interrupt line is selected for this interrupt bit
1 FIQ interrupt line is selected for this interrupt bit
Value Description
Number of physical endpoints implemented in this design
(excluding the default control endpoint). E.g. a value of 2 in
this field indicates that the design contains the default control
endpoint plus one IN endpoint (EP1 – IN) and one OUT
endpoint (EP1 – OUT)
EP single buffer supported
EP double buffer supported
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
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PN7462 family HW user manual
Reset
Value
0
Reset
Value
0
Reset
Value
0
Reset
Value
© NXP B.V. 2018. All rights reserved.
Access
R/W
Access
R/W
Access
R/W
Access
RO
RO
RO
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