General-Purpose Timers And Watchdog Timers; Timers Features (Timers 0 And 1); Timers Features (Timer 2 And 3); Watchdog Features - NXP Semiconductors PN7462 series User Manual

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NXP Semiconductors

11. General-purpose timers and watchdog timers

The PN7462 family includes two 12-bit general purpose timers (on LFO clock domain)
with match capabilities two 32-bit general purpose timers (on HFO clock domain) and a
Watch Dog Timer (WDT).
The purpose of the watchdog is to reset the microcontroller within a reasonable amount
of time if it enters an erroneous state. When enabled, the watchdog will generate a
system reset if the user program fails to 'feed' (or reload) the watchdog within a
predetermined amount of time.
The timers and watchdog are software configurable via a 32-bit APB slave interface.
Table 148. Timer characteristics
Name
Timer 0
Timer 1
Timer 2
Timer 3
Watchdog

11.1 Timers features (Timers 0 and 1)

• Two 12-bit counters
• 1 match register per timer, no capture registers and capture trigger pins are needed
• 1 common output line gathering the four timer (Timer0, Timer1, Timer2, Timer3)
• Timer0 and Timer1 can be concatenated (multiplied)
• Timer0 and Timer1 have two count modes: single-shot or free-running
• Timer0 and Timer1 timeout interrupts can be individually masked
• Timer0 and Timer1 Clock source is LFO clock

11.2 Timers features (Timer 2 and 3)

• Two 32-bit counters
• match register per timer, no capture registers and capture trigger pins are needed
• 1 common output line gathering the four timer (Timer0, Timer1, Timer2, Timer3)
• Timer2 and Timer3 have two count modes: single-shot or free-running
• Timer2 and Timer3 timeout interrupts can be individually masked
• Timer2 and Timer3 clock source is HFO Clock

11.3 Watchdog features

• The watchdog has 10-bit counter
UM10858
User manual
COMPANY PUBLIC
Clock
Frequency
source
LFO/2
190 KHz
LFO/2
190 KHz
HFO
20 MHz
HFO
20 MHz
LFO/128 2.96 KHz
Interrupts
Interrupts
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Counter
Resolution
length (bit)
(ms)
12
300 us
12
300 us
32
50 ns
32
50 ns
10
21.5 ms
314514
UM10858
PN7462 family HW user manual
Max
Chaining
delay(s)
possible
1.2
no
1.2
yes
214
no
214
no
22
no
© NXP B.V. 2018. All rights reserved.
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