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NXP Semiconductors
Bit
9
8
7:3
2
1
0
14.2.9.16 SPIM_INT_SET_STATUS_REG
This register is a collection of Set Interrupt Status commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 310. SPIM_INT_SET_STATUS_REG (address offset 0x3FEC)
Bit
31:10
9
8
7:3
2
1
0
UM10858
User manual
COMPANY PUBLIC
Symbol
AHB_ADDR_ERROR_CLR_
STATUS
AHB_ERROR_CLR_STATUS W
RESERVED
WATERLEVEL_REACHED_
CLR_STATUS
EOT_CLR_STATUS
EOR_CLR_STATUS
Symbol
RESERVED
AHB_ADDR_ERROR_SET_
STATUS
AHB_ERROR_SET_STATUS W
RESERVED
WATERLEVEL_REACHED_S
ET_STATUS
EOT_SET_STATUS
EOR_SET_STATUS
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Access Reset
Description
Value
W
0
1 - clear AHB address overflow Error
interrupt
0 – no effect
0
1 - clear AHB Slave Error interrupt
0 – no effect
W
0
Reserved
W
0
1 - clear water level reached interrupt
0 – no effect
W
0
1 - clear EOT interrupt
0 – no effect
W
0
1 - clear EOR interrupt
0 – no effect
Access Reset
Description
Value
W
0
Reserved
W
0
1 - set AHB address overflow Error
interrupt
0 – no effect
0
1 - set AHB Slave Error interrupt
0 – no effect
W
0
Reserved
W
0
1 - set water level reached interrupt
0 – no effect
W
0
1 - set EOT interrupt
0 – no effect
W
0
1 - set EOR interrupt
0 – no effect
UM10858
© NXP B.V. 2018. All rights reserved.
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