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18. List of figures
Fig 1.
Block diagram ................................................... 8
Fig 2.
Block diagram ................................................... 9
Fig 3.
Block diagram ................................................. 10
Fig 4.
PN7462 family Memory map ........................... 11
Fig 5.
APB memory map ........................................... 12
Fig 6.
Flash memory mapping .................................. 13
Fig 7.
EEPROM memory mapping ............................ 14
Fig 8.
SRAM memory mapping ................................. 15
Fig 9.
Block diagram of EEPROM/FLASH controller
module ............................................................ 16
Fig 10.
Powering the PN7462 family microcontroller .. 34
Fig 11.
Powering the contactless interface – using a
single power supply ........................................ 35
Fig 12.
Powering the contactless interface – using an
external RF transmitter supply ........................ 36
Fig 13.
Powering the contact interface ........................ 37
Fig 14.
Contact interface power supply connection
when the contact interface is not used ............ 37
Fig 15.
PMU Module, LDOs and power pins overview 38
Fig 16.
PN7462 family basic schematic ...................... 40
Fig 17.
Block diagram of PMU .................................... 42
Fig 18.
Clock generator block diagram ....................... 55
Fig 19.
27.12 MHz crystal oscillator connection .......... 56
Fig 20.
PLL/ XTAL clock path diagram ........................ 58
Fig 21.
Block diagram of PCR Unit ............................. 72
Fig 22.
Clock Box control ............................................ 78
Fig 23.
Clock gating .................................................... 80
Fig 24.
Block diagram of RNG module ...................... 125
Fig 25.
Communication diagram for ISO/IEC 14443 A
...................................................................... 135
Fig 26.
Data coding and framing according to ISO/IEC
14443 A card response ................................. 136
Fig 27.
ISO/IEC 14443B read/write mode
communication diagram ................................ 136
Fig 28.
FeliCa read/ write communication diagram ... 137
Fig 29.
RXMultiple data format ................................. 138
Fig 30.
ISO/IEC 15693 read/write mode communication
diagram ......................................................... 139
Fig 31.
Active communication mode ......................... 141
Fig 32.
Passive communication mode ...................... 142
Fig 33.
Contactless interface .................................... 147
Fig 34.
Lookup tables for AGC value dependent
dynamic configuration ................................... 196
Fig 35.
Transmitter supply voltage configuration,
V
> 3.5 V............................................ 197
DD(TVDD)
UM10858
User manual
COMPANY PUBLIC
Fig 36.
Fig 37.
Fig 38.
Fig 39.
Fig 40.
Fig 41.
Fig 42.
Fig 43.
Fig 44.
Fig 45.
Fig 46.
Fig 47.
Fig 48.
Fig 49.
Fig 50.
Fig 51.
Fig 52.
Fig 53.
Fig 54.
Fig 55.
Fig 56.
Fig 57.
Fig 58.
Fig 59.
Fig 60.
Fig 61.
Fig 62.
Fig 63.
Fig 64.
Fig 65.
Fig 66.
Fig 67.
Fig 68.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Contact Application schematics .................... 204
ATR counter timings checked (with default
values)........................................................... 207
Contact interface architecture ....................... 209
External TDA8026 connection ....................... 210
Registers overview per function .................... 214
ETU (and card clock CLK) generation ........... 217
I2C bus configuration .................................... 233
TX programming Flowchart ........................... 235
RX programming Flowchart ........................... 236
I2C external wiring diagram ........................... 238
I2C master transmitter example .................... 249
I2C master receiver example ........................ 250
Connection between SPI master and slaves . 251
SPI protocol with CPHA = 0 & NSS_PULSE = 0
...................................................................... 252
SPI protocol with CPHA = 1 & NSS_PULSE = 0
...................................................................... 253
SPI protocol with CPHA = 0 & NSS_PULSE = 1
...................................................................... 253
SPI packed structure ..................................... 254
RX data storage into memory. Defined/
undefined data .............................................. 254
TX CRC computation with
TX_CRC_PAYLOAD_OFFSET=1 and
TX_APPEND_CRC=1 ................................... 255
TX CRC computation with
TX_CRC_PAYLOAD_OFFSET=1 and
TX_APPEND_CRC=0 ................................... 256
RX CRC computation with
RX_CRC_PAYLOAD_OFFSET=1 ................ 256
Block diagram of Host interface block ........... 265
I2C Device ID Bit stream ............................... 269
SPI HDLL mode examples ............................ 271
SPI Native Mode (full duplex) ........................ 272
HSU byte transmission .................................. 274
HS UART bit correction ................................. 275
EOF_SIZE: max inter-byte delay and min inter-
frame delay ................................................... 276
RTS generation, frame based ....................... 277
HS UART-Buf_mgt protocol for transmit
sequence ....................................................... 279
Data-link layer frame format .......................... 283
USB block diagram ....................................... 315
USB software interface.................................. 316
© NXP B.V. 2018. All rights reserved.
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