NXP Semiconductors PN7462 series User Manual page 223

NXP Semiconductors
Bit Symbol Access
1 WARM R/W
0 START R/W
13.6.2.10 Register ct_ecr_reg (Early answer CounteR)
This configuration register enables to program the value of an 8-bit counter used to
check whether the card has answered too early.
Table 258. ct_ecr_reg (address 0024h) bit description
Bit Symbol Access
31:8 RESERVED -
7:0 EC7 - EC0 R/W
13.6.2.11 Register ct_mclr_lsb_reg (Mute card CounteR RST Low register Least Significant
Byte)
This configuration register is the least significant byte of a 16-bit counter used to check
whether the card answers when RST is logic 0.
Table 259. ct_mclr_lsb_reg (address 0028h) bit description
Bit Symbol Access
31:8 RESERVED -
7:0 MCL7 - MCL0 R/W
13.6.2.12 Register ct_mclr_msb_reg (Mute card CounteR RST Low register Most Significant
Byte)
This configuration register is the most significant byte of a 16-bit counter used to check
whether the card answers when RST is logic 0.
Table 260. ct_mclr_msb_reg (address 002Ch) bit description
Bit Symbol Access
31:8 RESERVED -
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Reset Description
Value
0b When set to logic 1: a warm reset procedure is started.
Set to logic 0 by hardware when a START bit is detected or when
MUTE bit is set to logic 1.
0b When set to logic 1: starts the activation sequence and cold reset
procedure (only if the PTL and PROTL bits in register ct_usr2_reg
are logic 0 and the PRES bit in register ct_msr_reg is logic 1).
When set to logic 0: starts the deactivation sequence.
Remark: the bits pres_pup_en and pres_con_no in ct_ssr_reg
register should have been set prior to any activation.
Reset Description
Value
0 reserved
1010 Early answer Counter
1010b
Programmable 8-bit clock counter (see ATR counter Functional Description).
Reset Description
Value
0 reserved
0111 Least significant byte of a programmable 16-bit clock counter (see
ATR counter Functional Description).
0100b
Reset Description
Value
0 reserved
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Rev. 1.4 — 14 May 2018
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