NXP Semiconductors PN7462 series User Manual page 341

NXP Semiconductors
Table 234. CLIF_ANA_TX_SHAPE_CONTROL_REG
register (address 0128h) ............................... 185
Table 235. CLIF_ANA_TEST_REG register (address
01FCh) .......................................................... 185
Table 236. CLIF_DPLL_INIT_REG register (address
0208h) ........................................................... 186
Table 237. CLIF_INT_CLR_ENABLE_REG register
(address 3FD8h) ........................................... 187
Table 238. CLIF_INT_SET_ENABLE_REG register
(address 3FDCh) .......................................... 189
Table 239. CLIF_INT_STATUS_REG register (address
3FE0h) .......................................................... 190
Table 240. CLIF_INT_ENABLE_REG register (address
3FE4h) .......................................................... 191
Table 241. CLIF_INT_CLR_STATUS_REG register
(address 3FE8h) ........................................... 193
Table 242. CLIF_INT_SET_STATUS_REG register
(address 3FECh) ........................................... 194
Table 243. DPC values ................................................... 197
Table 244. PCD Shaping entry definition ........................ 201
Table 245. Contact Smart card pins – Main slot ............. 205
Table 246. Contact Smart card pins – Auxiliary slots ...... 205
Table 247. Contact interface – Register overview (base
address 0x4001 4000) .................................. 210
Table 248. Register bit overview ..................................... 212
Table 249. Ct_ssr_reg (address 0000h) bit description .. 215
Table 250. ct_pdr1_lsb_reg/ct_pdr2_lsb_reg (address
0004h) bit description .................................... 216
Table 251. ct_pdr1_msb_reg/ct_pdr2_msb_reg (address
000Ch) bit description ................................... 216
Table 252. ct_fcr_reg (address 000Ch) bit description ... 217
Table 253. ct_gtr1_reg/ct_gtr2_reg (address 0010h) bit
description..................................................... 218
Table 254. ct_ucr11_reg/ct_ucr12_reg (address 0014h) bit
description..................................................... 219
Table 255. ct_ucr21_reg/ct_ucr22_reg (address 0018h) bit
description..................................................... 220
Table 256. ct_ccr1_reg/ct_ccr2_reg (address 001Ch) bit
description..................................................... 221
Table 257. ct_pcr_reg (address 0020h) bit description ... 222
Table 258. ct_ecr_reg (address 0024h) bit description ... 223
Table 259. ct_mclr_lsb_reg (address 0028h) bit description
...................................................................... 223
Table 260. ct_mclr_msb_reg (address 002Ch) bit
description..................................................... 223
Table 261. ct_mchr_lsb_reg (address 0030h) bit description
...................................................................... 224
Table 262. ct_mchr_msb_reg (address 0034h) bit
description..................................................... 224
Table 263. ct_ssr_reg (address 0038h) bit description ... 224
UM10858
User manual
COMPANY PUBLIC
Table 264. ct_urr_reg/ct_utr_reg (address 003Ch, 0040h,
Table 265. ct_tor1_reg (address 004Ch) bit description . 226
Table 266. ct_tor2_reg (address 0050h) bit description .. 226
Table 267. ct_tor3_reg (address 0054h) bit description .. 226
Table 268. ct_toc_reg (address 0058h) bit description ... 227
Table 269. Timer settings ................................................ 227
Table 270. ct_fsr_reg (address 005Ch) bit description.... 229
Table 271. ct_msr_reg (address 0060h) bit description .. 229
Table 272. ct_usr1_reg (address 0064h) bit description . 230
Table 273. ct_usr2_reg (address 0068h) bit description . 231
Table 274. I²C-bus pin description .................................. 234
Table 275. I2CM Register overview (base address 0x4003
Table 276. CONFIG_REG (address offset 0x0000) ........ 240
Table 277. BAUDRATE_REG (address offset 0x0004) .. 241
Table 278. SDA_HOLD_REG (address offset 0x0008)... 241
Table 279. I2C_ADDRESS_REG (address offset 0x000C)
Table 280. FIFO_THRESHOLD_REG (address offset
Table 281. BYTECOUNT_CONFIG_REG (address offset
Table 282. BYTECOUNT_STATUS_REG (address offset
Table 283. STATUS_REG (address offset 0x001C) ....... 243
Table 284. CONTROL_REG (address offset 0x0020) .... 243
Table 285. TX_DATA (address offset 0x0040 to 0x004C)
Table 286. RX_DATA (address offset 0x0050 to 0x005C)
Table 287. INT_CLR_ENABLE_REG (address offset
Table 288. INT_SET_ENABLE_REG (address offset
Table 289. INT_STATUS_REG (address offset 0x3FE0)246
Table 290. INT_ENABLE_REG (address offset 0x3FE4)246
Table 291. INT_CLR_STATUS_REG (address offset
Table 292. INT_SET_STATUS_REG (address offset
Table 293. SPI pin description ........................................ 252
Table 294. SPI master register overview (base address
Table 295. SPIM_STATUS_REG (address offset 0000h) bit
Table 296. SPIM_CONFIG_REG (address offset 0004h) bit
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Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
0044h, 0048h) bit description ........................ 225
0000) ............................................................. 238
...................................................................... 241
0x0010) ......................................................... 241
0x0014) ......................................................... 242
0x0018) ......................................................... 242
...................................................................... 244
...................................................................... 244
0x3FD8) ........................................................ 245
0x3FDC) ........................................................ 245
0x3FE8) ......................................................... 247
0x3FEC) ........................................................ 248
0x4003 4000) ................................................ 256
description ..................................................... 257
description ..................................................... 257
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