NXP Semiconductors PN7462 series User Manual page 230

NXP Semiconductors
Table 272. ct_usr1_reg (address 0064h) bit description
Bit Symbol Access
31:6 RESERVED -
5 MUTE R
4 EARLY R
3 pe R
2 ovr R
1 fer R
0 Ft R
Remark: When one of the bits ft, fer, ovr, pe, MUTE, EARLY is set at logic 1, then the
interrupt line is set at logic 1.
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Reset Description
Value
0 Reserved
During ATR, set to logic 1 when the card has not answered (it has not sent
0b
its ATR) within the time defined by the mute counter while RST was at logic
1 (see registers ct_mcrh_lsb_reg & ct_mcrh_msb_reg) or when the card has
answered while RST was at logic 0 (see registers ct_mcrl_lsb_reg &
ct_mcrl_lsb_reg).
Set to logic 0 after reading the byte.
0b During ATR, set to logic 1 when the card has answered two early within the
time defined by the early counter (see register ct_ecr_reg) while RST was at
logic 1 or when the card has answered while RST was at logic 0.
Set to logic 0 after reading the byte.
0b Parity Error
- In protocol T=0, it is high if the character has been received with parity
error a number of time equals to the number written in PEC(2:0) of register
ct_fcr_reg +1 or if the transmitted character has been NAKed by the card a
number of times equal to the value programmed in bits PEC(2:0) +1. It is set
at 10.5 ETU in the reception mode and at 11.5 ETU in the transmission
mode. A character received with a parity error is not stored into the FIFO
and the card is supposed to repeat this character.
- In protocol T=1, it is high when the parity error has been detected.
A character with a parity error is stored into the FIFO and the parity error
counter is not active.
Set to logic 0 after reading the byte.
0b OVerRun
Set to logic 1 when a new character has been received whilst the FIFO was
full. In this case, at least one character has been lost.
Set to logic 0 after reading the byte.
0b Framing ERror
Set to logic 1 when the I/O line was not in the high-impedance state at 10.25
ETUs after a start bit.
Set to logic 0 after reading the byte.
0b Fifo Threshold
Set to logic 1 in reception mode if the number of received bytes in the FIFO
equals to the number written in bits ft(4:0) + 1 of the register ct_fcr_reg. This
bit goes high 10.5 ETUs after the start bit of the (ft(4:0) + 1)th received
character. In transmission mode, it is set to logic 1 when the number of
remaining bytes to transmit in the FIFO equals to the number written in bits
ft(4:0) of the register ct_fcr_reg. This bit goes high 9.5 ETUs after the start
bit of the (32 - ft(4:0))th transmitted character.
Set to logic 0 after reading the byte.
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Rev. 1.4 — 14 May 2018
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