NXP Semiconductors PN7462 series User Manual page 240

NXP Semiconductors
14.1.9 Register description
14.1.9.1 CONFIG_REG
This register is used to configure the I2C master.
Table 276. CONFIG_REG (address offset 0x0000)
Legend: * reset value; <= mandatory value
Bit Symbol
31:5 RESERVED
4 RESET_I2C_CORE
3 RESET_REG
2 FIFO_FLUSH
1 SLV_ADDRESSING
0 IP_MODE
IP_MODE
IP_MODE bit field determines the I2C master mode of operation.
SLV_ADDRESSING
SLV_ADDRESSING bit field determines I2C master slave addressing.
FIFO_FLUSH
Writing 1 to the FIFO_FLUSH bit field will generate a pulse to flush the content of the
FIFO irrespective of I2C master mode of operation.
RESET_REG
Writing 1 to the RESET_REG bit field will generate a pulse to reset the following registers
to their default value.
1. BAUDRATE_REG
2. SDAHOLD_REG
3. I2C_ADDRESS_REG
4. FIFO_THRESHOLD_REG
5. BYTECOUNT_CONFIG_REG
RESET_I2C_CORE
Writing 1 to the RESET_I2C_CORE bit field will generate a pulse to reset the I2C Core
block/state-machine.
UM10858
User manual
COMPANY PUBLIC
Access Value
R 0x0000000*
-X 0x0*
-X 0x0*
-X 0x0*
R/W 0x0*
R/W 0x0*
•
IP_MODE = 0x0: I2Cmaster as transmitter
•
IP_MODE = 0x1: I2C master as receiver
•
SLV_ADDRESSING = 0x0: 7-bit I2C slave addressing
•
SLV_ADDRESSING = 0x1: 10-bit I2C slave addressing
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
reserved
Set Only (Pulse) Register Bit Field to Reset the I
Block.
Set Only (Pulse) Register Bit Field to Reset Selected
2
Registers of I C Master
Set Only (Pulse) Register Bit Field to flush the FIFO
2
irrespective of I C Master Mode of operation
2
I C Slave 7/10 bit address selection
2
I C Master Mode selection
UM10858
2
C Core
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