NXP Semiconductors PN7462 series User Manual page 63

NXP Semiconductors
Bit Symbol
1 USB_PLL_LOCK_OVERRIDEN
0 USB_PLL_LOCK
7.5.1 Oscillators register description
Oscillators are controlled by the registers shown in
follow. Writes to any unused bits are ignored.
Table 53. Oscillators Registers
Name
CLKGEN_HFO_XTAL_REG
CLKGEN_HFO_TRIM_REG
7.5.1.1 HFO and XTAL control register
The CLKGEN_HFO_XTAL_REG register contains the bits that Activate/Enable XTAL,
enable HFO.
Table 54. CLKGEN_HFO_XTAL_REG (address 0004h)
Bit Symbol
31:24 RESERVED
23:12 XTAL_ACTIVATION_TIMEOUT R/W
11 XTAL_DETECT_ENABLE
10 XTAL_SPARE3
9 XTAL_SPARE2
8 XTAL_SPARE1
7 XTAL_SPARE0
UM10858
User manual
COMPANY PUBLIC
Access Value
R 0
R 0
Address Width Access
offset (bits)
0004h 32 R/W
0008h 32 R/W
Access Value Description
R/W 0x00 Reserved
Set the XTAL activation timeout value (in LFO Clock
0xFFF
Cycles + 8); Default value > 10 ms
R/W 0x00 Enables the XTAL output clock presence detection if
clk_in_detect_enable is low.
1: Enable XTAL clk detection
0: Disable XTAL clk detection
R/W 0x00 controls XTAL Spare3
R/W 0x00 controls XTAL Spare2
R/W 0x00 controls XTAL Spare1
R/W 0x00 controls XTAL Pull Down
1: enable strong pull-down on clk_xtal port of clkgen_ana
sub-block
0: disable pull-down on clk_xtal port of clkgen_ana sub-
block
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
Acknowledged
0: No feedback divider ratio change
USB_PLL lock overriden status
1: CLKGEN_STATUS_REG.USB_PLL_lock or
CLKGEN_USB_PLL_GLOBAL_CONTROL_REG.USB_
PLL_lock_bypass is high.
0: USB PLL Lock is not set
USB_PLL lock status
1: USB PLL lock set
0: USB PLL lock is not set
Table 53. More detailed descriptions
Reset value Description
00FFF001h HFO and XTAL control register
00000000h HFO trimming value register
UM10858
© NXP B.V. 2018. All rights reserved.
63 of 345