NXP Semiconductors PN7462 series User Manual page 219

NXP Semiconductors
13.6.2.6 Register ct_ucr11_reg/ct_ucr12_reg (UART Configuration Register 1)
This configuration register defines the reception and transmission settings.
This register is doubled: ct_ucr11_reg is dedicated to the full slot and ct_ucr12_reg is
dedicated to the auxiliary slot. Both registers share the same address, the selection is
done via bit IOauxen of register ct_ssr_reg.
Table 254. ct_ucr11_reg/ct_ucr12_reg (address 0014h) bit description
Bit Symbol Access
31:6 RESERVED -
5 FIP R/W
4 FC R/W
3 PROT R/W
2 T/R R/W
1 LCT R/W
0 CONV R/W
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Reset Description
Value
0 Reserved
0b Force Inverse Parity
If bit FIP is set to logic 1, the Contact UART will NAK a correctly received
character, and will transmit characters with wrong parity bits.
0b
0b PROTocol
Selects the protocol: logic 1 means T=1 and logic 0 T=0.
0b Transmit/Receive
Defines the mode: logic 1 means transmission and logic 0 reception.
Bit T/R is set by software for transmission mode. Bit T/R is automatically reset
to logic 0 by hardware, if bit LCT has been used before transmitting the last
character.
Note that when switching from/to reception to/from transmission mode, the
FIFO is flushed. Any remaining bytes are lost.
0b Last Character to Transmit
Bit LCT is set to logic 1 by software before writing the last character to be
transmitted in register ct_utr_reg. It allows automatic change to reception mode.
It is reset to logic 0 by hardware at the end of a successful transmission after
11.75 ETUs in protocol T = 0 and after 10.75 ETUs in protocol T = 1. When bit
LCT is being reset to logic 0, bit T/R is also reset to logic 0 and the UART is
ready to receive a character.
LCT bit can be set to logic 1 by software not only when writing the last
character to be transmitted but also during the transmission or even at the
beginning of the transmission. It will be taken into account when the FIFO
becomes empty, which implies for the software to be able to regularly re-load
the FIFO when transmitting more than 32 bytes to ensure there is at least one
byte into the FIFO as long as the transmission is not finished. Else, a switch to
reception mode will prematurely occur before having transmitted all the bytes.
0b CONVention
Bit CONV is set to logic 1 if the convention is direct. Bit CONV is either
automatically written by hardware according to the convention detected during
ATR, or by software if the bit AUTOCONV in register ct_ucr1_reg is set to logic
1.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
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