NXP Semiconductors P89LPC980 User Manual
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NXP Semiconductors P89LPC980 User Manual

NXP Semiconductors P89LPC980 User Manual

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UM10346
LPC980/982 User manual
Rev. 01 — 2 November 2009
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P89LPC980/982
Abstract
Technical information for the P89LPC980/982 device
User manual

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Summary of Contents for NXP Semiconductors P89LPC980

  • Page 1 UM10346 LPC980/982 User manual Rev. 01 — 2 November 2009 User manual Document information Info Content Keywords P89LPC980/982 Abstract Technical information for the P89LPC980/982 device...
  • Page 2 UM10346 NXP Semiconductors LPC980/982 User manual Revision history Date Description 20091102 Initial version. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10346_1 © NXP B.V. 2009. All rights reserved. User manual Rev.

  • Page 3: Introduction

    80C51 devices. Many system-level functions have been incorporated into the P89LPC980/982 in order to reduce component count, board space, and system cost.

  • Page 4: Pin Description

    UM10346 NXP Semiconductors LPC980/982 User manual P1.6/MISO P0.2/CIN2A/KBI2 P1.5/RST P0.3/CIN1B/KBI3/T2 P0.4/CIN1A/KBI4 P3.1/XTAL1 P0.5/CMPREF/KBI5/T3 P89LPC982 P3.0/XTAL2/CLKOUT P0.6/CMP1/KBI6 P1.4/INT1/T4EX/SS P0.7/T1/KBI7 P1.3/INT0/SDA/T4 002aae538 Fig 2. P89LPC982 PLCC28 pin configuration 1.2 Pin description Table 1. Pin description Symbol Type Description PLCC28, TSSOP28 P0.0 to P0.7 Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.
  • Page 5 UM10346 NXP Semiconductors LPC980/982 User manual Table 1. Pin description …continued Symbol Type Description PLCC28, TSSOP28 P0.1/CIN2B/ P0.1 — Port 0 bit 1. KBI1 CIN2B — Comparator 2 positive input B. KBI1 — Keyboard input 1. P0.2/CIN2A/ P0.2 — Port 0 bit 2.
  • Page 6 UM10346 NXP Semiconductors LPC980/982 User manual Table 1. Pin description …continued Symbol Type Description PLCC28, TSSOP28 P0.6/CMP1/KBI6 P0.6 — Port 0 bit 6. High current source. CMP1 — Comparator 1 output. KBI6 — Keyboard input 6. P0.7/KBI7/T1 P0.7 — Port 0 bit 7. High current source.
  • Page 7 UM10346 NXP Semiconductors LPC980/982 User manual Table 1. Pin description …continued Symbol Type Description PLCC28, TSSOP28 P1.7/T3EX/MOSI P1.7 — Port 1 bit 7. High current source. T3EX — Timer/counter 3 external capture input. MOSI — SPI master out slave in. When configured as master, this pin is output;...
  • Page 8 UM10346 NXP Semiconductors LPC980/982 User manual Table 1. Pin description …continued Symbol Type Description PLCC28, TSSOP28 P3.1/XTAL1 P3.1 — Port 3 bit 1. XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer.

  • Page 9: Logic Symbols

    P89LPC980/982 CLKOUT XTAL2 PORT 3 MOSI XTAL1 MISO PORT 2 SPICLK 002aae534 (1) For Pin Remap. Fig 3. P89LPC980/982 logic symbol UM10346_1 © NXP B.V. 2009. All rights reserved. User manual Rev. 01 — 2 November 2009 9 of 132...

  • Page 10: Block Diagram

    POWER MANAGEMENT CRYSTAL OSCILLATOR CONFIGURABLE (POWER-ON RESET, OSCILLATOR WITH CLOCK BROWNOUT RESET, RESONATOR XTAL2 DOUBLER REGULATORS) 002aae532 Fig 4. P89LPC980/982 Block diagram UM10346_1 © NXP B.V. 2009. All rights reserved. User manual Rev. 01 — 2 November 2009 10 of 132...

  • Page 11: Special Function Registers

    UM10346 NXP Semiconductors LPC980/982 User manual 1.5 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
  • Page 12 Table 2. Special function registers - P89LPC980/982 * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value addr.
  • Page 13 Table 2. Special function registers - P89LPC980/982 * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value addr.
  • Page 14 Table 2. Special function registers - P89LPC980/982 * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value addr.
  • Page 15 Table 2. Special function registers - P89LPC980/982 * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value addr.
  • Page 16 Table 2. Special function registers - P89LPC980/982 * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value addr.
  • Page 17 Table 2. Special function registers - P89LPC980/982 * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value addr.
  • Page 18 Table 2. Special function registers - P89LPC980/982 * indicates SFRs that are bit addressable. Name Description Bit functions and addresses Reset value addr.
  • Page 19 On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset sources that affect these SFRs are power-on reset and watchdog reset. Table 3. Extended special function registers - P89LPC980/982 Name Description...

  • Page 20: Memory Organization

    0000h (P89LPC982) 0000h 002aae986 (1) ISP code is located at the end of sector 3 on the P89LPC980 and at the endof sector 7 on P89LPC982. Fig 5. P89LPC980/982 memory map The various P89LPC980/982 memory spaces are as follows: DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC.

  • Page 21: Clocks

    2. Clocks 2.1 Enhanced CPU The P89LPC980/982 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

  • Page 22: Crystal Oscillator Option

    TRIM register. 2.5 On-chip RC oscillator option The P89LPC980/982 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. (Note: the initial value is better than 1 %;...

  • Page 23: Watchdog Oscillator Option

    UM10346 NXP Semiconductors LPC980/982 User manual Table 5. On-chip RC oscillator trim register (TRIM - address 96h) bit allocation Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 Reset Bits 5:0 loaded with factory stored value during reset. Table 6.

  • Page 24: Clock Source Switching On The Fly

    Block diagram of oscillator control 2.8 Clock source switching on the fly P89LPC980/982 can implement clock switching on any sources of watchdog oscillator, 7/14MHz IRC oscillator, crystal oscillator and external clock input during code is running. CLKOK bit in register CLKCON is read only and used to indicate the clock switch status.

  • Page 25: Oscillator Clock (Oscclk) Wake-Up Delay

    High frequency crystal or resonator, 4 MHz to 18 MHz. 2.9 Oscillator Clock (OSCCLK) wake-up delay The P89LPC980/982 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 μs to 100 μs.

  • Page 26: Low Power Select

    2.11 Low power select The P89LPC980/982 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further.

  • Page 27: Interrupt Priority Structure

    IPx and IPxH (x = 0, 1) and can therefore be assigned to one of four levels, as shown in Table The P89LPC980/982 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.
  • Page 28 UM10346 NXP Semiconductors LPC980/982 User manual Table 11. Summary of interrupts Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power- bit(s) address bit(s) priority ranking down wake-up External interrupt 0 0003h EX0 (IEN0.0) IP0H.0, IP0.0 1 (highest) Timer 0 interrupt 000Bh ET0 (IEN0.1)

  • Page 29: I/O Ports

    4. I/O ports The P89LPC980/982 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1,and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends...

  • Page 30: Port Configurations

    (external crystal or resonator) External RST pin supported 4.1 Port configurations All but three I/O port pins on the P89LPC980/982 may be configured by software to one of four types on a pin-by-pin basis, as shown in Table 13. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only.

  • Page 31: Open Drain Output Configuration

    The quasi-bidirectional port configuration is shown in Figure Although the P89LPC980/982 is a 3 V device most of the pins are 5 V-tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V causing extra power consumption.

  • Page 32: Input-Only Configuration

    4.4 Input-only configuration The input port configuration is shown in Figure 11. It is a Schmitt-triggered input that also has a glitch suppression circuit. (Please refer to the P89LPC980/982 data sheet, Dynamic characteristics for glitch filter specifications). input port data...

  • Page 33: Port 0 And Analog Comparator Functions

    Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open drain. Every output on the P89LPC980/982 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded.

  • Page 34: Pin Remap

    UM10346 NXP Semiconductors LPC980/982 User manual Table 14. Port output configuration Port pin Configuration SFR bits PxM1.y PxM2.y Alternate usage Notes P0.0 P0M1.0 P0M2.0 KBI0, CMP2, SPICLK P0.1 P0M1.1 P0M2.1 KBI1, CIN2B Refer to Section 4.6 “Port 0 and Analog Comparator functions”...

  • Page 35: Power Management

    Power-on detect and brownout detect are designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. The P89LPC980/982 support three different power reduction modes: Idle mode, Power-down mode, and total Power-down mode. In addition, individual on-chip peripherals can be disabled to eliminate unnecessary dynamic power use in any peripherals that are not required for the application.
  • Page 36 UM10346 NXP Semiconductors LPC980/982 User manual These 3 functions are disabled in Power-down mode and Total Power-down mode. In normal or idle mode, BOD reset and BOD flash are always on and can not be disabled in software. BOD interrupt will generate an interrupt and could be enabled or disabled in software.

  • Page 37: Power-On Detection

    RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software. 5.3 Power reduction modes The P89LPC980/982 supports three different power reduction modes as determined by SFR bits PCON[1:0] (see Table 21).
  • Page 38 The Power-down mode stops the oscillator in order to minimize power consumption. Brownout circuitry is disabled. The P89LPC980/982 exits Power-down mode via any reset, or certain interrupts - external pins INT0/INT1, keyboard, Real-time Clock/System Timer), watchdog, and comparator trips. Waking up by reset is only enabled if the corresponding reset is enabled, and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit (IEN0.7) is set.
  • Page 39 UM10346 NXP Semiconductors LPC980/982 User manual Table 23. Power Control register (PCON - address 87h) bit description Symbol Description PMOD0 Power Reduction Mode (see Section 5.3) PMOD1 General Purpose Flag 0. May be read or written by user software, but has no effect on operation General Purpose Flag 1.

  • Page 40: Regulators

    RPE bit. Other sources of reset will not override the RPE bit. Note: During a power cycle, V must fall below V (see P89LPC980/982 data sheet, Static characteristics) before power is reapplied, in order to ensure a power-on reset. Reset can be triggered from the following sources: •...
  • Page 41 UM10346 NXP Semiconductors LPC980/982 User manual • Brownout detect; • Watchdog timer; • Software reset; • UART break character detect reset. For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a ‘0’...

  • Page 42: Reset Vector

    6.1 Reset vector Following reset, the P89LPC980/982 will fetch instructions from either address 0000h or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address = 00h. The Boot address will be used if a UART break reset occurs or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the...

  • Page 43: Mode 0

    UM10346 NXP Semiconductors LPC980/982 User manual Table 31. Timer/Counter Mode register (TMOD - address 89h) bit description Bit Symbol Description T0M0 Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the...

  • Page 44: Mode 1

    Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P89LPC980/982 device can look like it has three Timer/Counters. Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3.
  • Page 45 UM10346 NXP Semiconductors LPC980/982 User manual Note that interrupt can still be enabled on the low to high transition of TFn, and that TFn can still be cleared in software like in any other modes. Table 34. Timer/Counter Control register (TCON) - address 88h) bit allocation...
  • Page 46 UM10346 NXP Semiconductors LPC980/982 User manual overflow C/T = 0 PCLK interrupt Tn pin (8-bits) (8-bits) control C/T = 1 toggle Tn pin Gate INTn pin ENTn 002aaa920 Fig 15. Timer/counter 0 or 1 in mode 1 (16-bit counter) C/T = 0...

  • Page 47: Timer Overflow Toggle Output

    PCLK as the clock source for the timer. 8. Timers 2, 3 and 4 The P89LPC980/982 has three external 16-bit timers/counters. All can be configured to operate either as timers or event counters. An option to automatically toggle the Tx pin upon timer overflow has been added.
  • Page 48 UM10346 NXP Semiconductors LPC980/982 User manual Table 37. Timer/Counter x Control(TxCON - where x = 2, 3 or 4) bit description Bit Symbol Description CP/NRLx Capture/Reload control. When set, captures occur on 1-to-0 transitions of TxEX (if EXENx is set). When cleared, auto-reloads are performed on timer overflows or on negative transitions of TxEX (if EXENx is set).

  • Page 49: Mode 0: 16-Bit Timer/Counter With Auto-Reload

    UM10346 NXP Semiconductors LPC980/982 User manual Table 40. Data Register Map Lable Description Address Reset Value Timer/Counter 2 High Byte Timer/Counter 2 Low Byte RCAP2H Capture Register 2 High Byte RCAP2L Capture Register 2 Low Byte PWMD2H PWM Free Cycle Register 2 High Byte...

  • Page 50: Mode 1: 16-Bit Timer/Counter With Input Capture

    UM10346 NXP Semiconductors LPC980/982 User manual C/NTx = 0 PCLK (8-bits) (8-bits) Tx pin reload toggle RCAPxL RCAPxL Tx pin ENTx transition detector timer x TxEX pin EXFx interrupt 002aae545 EXENx Fig 19. 16-bit Timer/Counter Auto-reload Mode 8.2 Mode 1: 16-bit Timer/Counter with Input Capture...

  • Page 51: Mode 2: 16-Bit Pwm Mode

    UM10346 NXP Semiconductors LPC980/982 User manual C/NTx = 0 PCLK (8-bits) (8-bits) Tx pin capture RCAPxL RCAPxH transition detector timer x TxEX pin EXFx interrupt 002aae546 EXENx Fig 20. 16-bit Timer/Counter Input Capture Mode 8.3 Mode 2: 16-bit PWM mode In PWM mode, the corresponding timer can be configured as a PWM generator, and the RCAPxH and RCAPxL registers are also used as PWM duty cycle registers.

  • Page 52: Timer Overflow Toggle Output

    PCLK as the clock source for the timer. 9. Real-time clock system timer The P89LPC980/982 has a simple Real-time Clock/System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down. The...

  • Page 53: Real-Time Clock Source

    UM10346 NXP Semiconductors LPC980/982 User manual Power-on reset XTAL2 XTAL1 RTCH RTCL RTC Reset Reload on underflow LOW FREQ. MED. FREQ. HIGH FREQ. 7-bit prescaler 23-bit down counter ÷128 CCLK internal RTCDATH RTCDATL oscillators Wake-up from power-down RTCS1 RTCS2 RTCF...
  • Page 54 UM10346 NXP Semiconductors LPC980/982 User manual Table 41. Real-time Clock/System Timer clock sources FOSC2:0 RCCLK RTCS1:0 RTC clock source CPU clock source High frequency crystal High frequency crystal /DIVM High frequency crystal /DIVM High frequency crystal Internal RC oscillator Internal RC oscillator...
  • Page 55 UM10346 NXP Semiconductors LPC980/982 User manual Table 41. Real-time Clock/System Timer clock sources …continued FOSC2:0 RCCLK RTCS1:0 RTC clock source CPU clock source High frequency crystal Watchdog oscillator /DIVM Medium frequency crystal Low frequency crystal Watchdog oscillator /DIVM High frequency crystal...

  • Page 56: Uart

    LPC980/982 User manual 10. UART The P89LPC980/982 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC980/982 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator.

  • Page 57: Baud Rate Generator And Selection

    Baud Rate Generator Control 10.6 Baud Rate generator and selection The P89LPC980/982 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a value programmed into the BRGR1 and BRGR0 SFRs. The UART can use either Timer 1 or the baud rate generator output as determined by...

  • Page 58: Framing Error

    UM10346 NXP Semiconductors LPC980/982 User manual Table 47. Baud Rate Generator Control register (BRGCON - address BDh) bit description Bit Symbol Description BRGEN Baud Rate Generator Enable. Enables the baud rate generator. BRGR1 and BRGR0 can only be written when BRGEN = 0.
  • Page 59 UM10346 NXP Semiconductors LPC980/982 User manual Table 49. Serial Port Control register (SCON - address 98h) bit description …continued Bit Symbol Description The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

  • Page 60: More About Uart Mode 0

    UM10346 NXP Semiconductors LPC980/982 User manual Table 52. Serial Port Status register (SSTAT - address BAh) bit description …continued Bit Symbol Description DBISEL Double buffering transmit interrupt select. Used only if double buffering is enabled. This bit controls the number of interrupts that can occur when double buffering is enabled.

  • Page 61: More About Uart Mode 1

    UM10346 NXP Semiconductors LPC980/982 User manual S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ...

  • Page 62: More About Uart Modes 2 And 3

    UM10346 NXP Semiconductors LPC980/982 User manual TX clock write to SBUF transmit shift start stop bit INTLO = 0 INTLO = 1 clock start ÷16 reset stop bit receive shift 002aaa926 Fig 26. Serial Port Mode 1 (only single transmit buffering case is shown) 10.12 More about UART Modes 2 and 3...

  • Page 63: Break Detect

    UM10346 NXP Semiconductors LPC980/982 User manual Table 53. FE and RI when SM2 = 1 in Modes 2 and 3 Mode PCON.6 (SMOD0) No RI when RB8 = 0 Occurs during STOP Similar to Figure 27, with SMOD0 = 0, RI...

  • Page 64: The 9Th Bit (Bit 8) In Double Buffering (Modes 1, 2, And 3)

    UM10346 NXP Semiconductors LPC980/982 User manual – If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter (which is also the last data).

  • Page 65: Multiprocessor Communications

    UM10346 NXP Semiconductors LPC980/982 User manual If double buffering is enabled, TB8 MUST be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. The operation described in the Section 10.17 “Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)”...

  • Page 66: Automatic Address Recognition

    UM10346 NXP Semiconductors LPC980/982 User manual 10.20 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port.

  • Page 67: C Interface

    I C-bus will not be released. The P89LPC980/982 device provides a byte-oriented I C interface. It has four operation modes: Master Transmitter Mode, Master Receiver Mode, Slave Transmitter Mode and Slave Receiver Mode.

  • Page 68: C Data Register

    P89LPC980/982 INTERFACE INTERFACE 002aae984 Fig 29. I C-bus configuration The P89LPC980/982 CPU interfaces with the I C-bus through six Special Function Registers (SFRs): I2CON (I C Control Register), I2DAT (I C Data Register), I2STAT (I Status Register), I2ADR (I C Slave Address Register), I2SCLH (SCL Duty Cycle Register High Byte), and I2SCLL (SCL Duty Cycle Register Low Byte).

  • Page 69: C Control Register

    UM10346 NXP Semiconductors LPC980/982 User manual 11.3 I C control register The CPU can read and write this register. There are two bits are affected by hardware: the SI bit and the STO bit. The SI bit is set by hardware and the STO bit is cleared by hardware.

  • Page 70: C Status Register

    UM10346 NXP Semiconductors LPC980/982 User manual Table 60. C Control register (I2CON - address D8h) bit description …continued Bit Symbol Description C Interrupt Flag. This bit is set when one of the 25 possible I C states is entered. When EA bit and EI2C (IEN1.0) bit are both set, an interrupt is requested when SI is set.

  • Page 71: I 2 C Operation Modes

    UM10346 NXP Semiconductors LPC980/982 User manual The values for I2SCLL and I2SCLH do not have to be the same; the user can give different duty cycles for SCL by setting these two registers. However, the value of the register must ensure that the data rate is in the I C data rate range of 0 to 400 kHz.

  • Page 72: Master Receiver Mode

    UM10346 NXP Semiconductors LPC980/982 User manual The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.

  • Page 73: Slave Receiver Mode

    UM10346 NXP Semiconductors LPC980/982 User manual slave address DATA DATA logic 0 = write data transferred logic 1 = read (n Bytes + acknowledge) A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) from Master to Slave S = START condition...

  • Page 74: Slave Transmitter Mode

    UM10346 NXP Semiconductors LPC980/982 User manual slave address DATA DATA P/RS logic 0 = write data transferred logic 1 = read (n Bytes + acknowledge) A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) from Master to Slave...
  • Page 75 UM10346 NXP Semiconductors LPC980/982 User manual I2ADR ADDRESS REGISTER P1.3 COMPARATOR INPUT FILTER P1.3/SDA SHIFT REGISTER OUTPUT STAGE I2DAT BIT COUNTER / ARBITRATION & CCLK INPUT TIMING SYNC LOGIC FILTER CONTROL P1.2/SCL LOGIC SERIAL CLOCK OUTPUT interrupt GENERATOR STAGE timer 1...
  • Page 76 UM10346 NXP Semiconductors LPC980/982 User manual Table 66. Master Transmitter mode Status code Status of the I Application software response Next action taken by I (I2STAT) hardware hardware to/from I2DAT to I2CON A START Load SLA+W SLA+W will be transmitted;...
  • Page 77 UM10346 NXP Semiconductors LPC980/982 User manual Table 66. Master Transmitter mode …continued Status code Status of the I Application software response Next action taken by I (I2STAT) hardware hardware to/from I2DAT to I2CON Data byte in Load data byte or 0 Data byte will be transmitted;...
  • Page 78 UM10346 NXP Semiconductors LPC980/982 User manual Table 67. Master Receiver mode …continued Status code Status of the I Application software response Next action taken by I C hardware (I2STAT) hardware to/from I2DAT to I2CON STA STO SI Data byte has Read data byte Data byte will be received;...
  • Page 79 UM10346 NXP Semiconductors LPC980/982 User manual Table 68. Slave Receiver mode …continued Status code Status of the I Application software response Next action taken by I (I2STAT) hardware hardware to/from I2DAT to I2CON STO SI Previously Read data byte or 0...
  • Page 80 UM10346 NXP Semiconductors LPC980/982 User manual Table 68. Slave Receiver mode …continued Status code Status of the I Application software response Next action taken by I (I2STAT) hardware hardware to/from I2DAT to I2CON STO SI A STOP condition No I2DAT action...

  • Page 81: Serial Peripheral Interface (Spi)

    12. Serial Peripheral Interface (SPI) The P89LPC980/982 provides another high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master or Slave mode.
  • Page 82 UM10346 NXP Semiconductors LPC980/982 User manual MISO P2.3 CPU clock 8-BIT SHIFT REGISTER MOSI P2.2 READ DATA BUFFER CONTROL DIVIDER BY 4, 16, 64, 128 LOGIC SPICLK P2.5 clock SPI clock (master) SELECT CLOCK LOGIC P2.4 MSTR SPEN SPI CONTROL...
  • Page 83 UM10346 NXP Semiconductors LPC980/982 User manual Table 71. SPI Control register (SPCTL - address E2h) bit description Bit Symbol Description SPR0 SPI Clock Rate Select SPR1, SPR0: SPR1 ⁄ CCLK 00 — ⁄ CCLK 01 — ⁄ CCLK 10 —...
  • Page 84 UM10346 NXP Semiconductors LPC980/982 User manual Table 74. SPI Data register (SPDAT - address E3h) bit allocation Symbol Reset master slave MISO MISO 8-BIT SHIFT 8-BIT SHIFT MOSI MOSI REGISTER REGISTER SPICLK SPICLK SPI CLOCK PORT GENERATOR 002aaa901 Fig 37. SPI single master single slave configuration Figure 37, SSIG (SPCTL.7) for the slave is logic 0, and SS is used to select the slave.

  • Page 85: Configuring The Spi

    UM10346 NXP Semiconductors LPC980/982 User manual master slave MISO MISO 8-BIT SHIFT 8-BIT SHIFT MOSI MOSI REGISTER REGISTER SPICLK SPICLK SPI CLOCK port GENERATOR slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK port 002aaa903 Fig 39. SPI single master multiple slaves configuration Figure 39, SSIG (SPCTL.7) bits for the slaves are logic 0, and the slaves are selected...

  • Page 86: Additional Considerations For A Slave

    UM10346 NXP Semiconductors LPC980/982 User manual Table 75. SPI master and slave selection …continued SPEN SSIG SS Pin MSTR Master MISO MOSI SPICLK Remarks or Slave Mode Master input Hi-Z Hi-Z MOSI and SPICLK are at high-impedance to avoid bus contention when the MAster is idle.

  • Page 87: Write Collision

    UM10346 NXP Semiconductors LPC980/982 User manual slave and start sending data to it. To avoid bus contention, the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be an input and MISO becomes an output.
  • Page 88 UM10346 NXP Semiconductors LPC980/982 User manual Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) 002aaa934 (1) Not defined Fig 40.
  • Page 89 UM10346 NXP Semiconductors LPC980/982 User manual Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) 002aaa935 (1) Not defined Fig 41.
  • Page 90 UM10346 NXP Semiconductors LPC980/982 User manual Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) 002aaa936 (1) Not defined Fig 42.

  • Page 91: Spi Clock Prescaler Select

    71). 13. Analog comparators Two analog comparators are provided on the P89LPC980/982. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage).
  • Page 92 UM10346 NXP Semiconductors LPC980/982 User manual When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

  • Page 93: Selectable Internal Reference Voltage

    Comparator Reference register (CMPREF). Each of the two comparators may use a different reference voltage. Please refer to the P89LPC980/982 data sheet for specifications. Table 78. Comparator Reference register (CMPREF - address FFCBh) bit allocation...

  • Page 94: Comparator Input Pins

    Comparator input and reference pins maybe be used as either digital I/O or as inputs to the comparator. However, when selected as comparator input signals in CMPn lower voltage limits apply. Please refer to the P89LPC980/982 data sheet for specifications. 13.4 Comparator interrupt Each comparator has an interrupt flag CMFn contained in its configuration register.

  • Page 95: Comparators Configuration Example

    UM10346 NXP Semiconductors LPC980/982 User manual Comparators consume power in Power-down mode and Idle mode, as well as in the normal operating mode. This should be taken into consideration when system power consumption is an issue. To minimize power consumption, the user can power-down the comparators by disabling the comparators and setting PCONA.5 to logic 1, or simply...

  • Page 96: Keypad Interrupt (Kbi)

    UM10346 NXP Semiconductors LPC980/982 User manual The interrupt routine used for the comparator must clear the interrupt flag (CMF1 in this case) before returning 14. Keypad interrupt (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern.

  • Page 97: Watchdog Timer (Wdt)

    UM10346 NXP Semiconductors LPC980/982 User manual Table 83. Keypad Control register (KBCON - address 94h) bit description Bit Symbol Access Description KBIF Keypad Interrupt Flag. Set when Port 0 matches user defined conditions specified in KBPATN, KBMASK, and PATN_SEL. Needs to be cleared by software by writing logic 0.
  • Page 98 UM10346 NXP Semiconductors LPC980/982 User manual When the timer is not enabled to reset the device on underflow, the WDT can be used in ‘timer mode’ and be enabled to produce an interrupt (IEN0.6) if desired. The Watchdog Safety Enable bit, WDSE (UCFG2.1) along with WDTE, is designed to force certain operating conditions at power-up.

  • Page 99: Feed Sequence

    SETB EA ;enable interrupt This sequence assumes that the P89LPC980/982 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence. If an interrupt was allowed to be serviced and the service routine contained any SFR writes, it would trigger a watchdog reset.
  • Page 100 The minimum number of tclks is: tclks The maximum number of tclks is: ) 255 tclks 1048577 Table 89 shows sample P89LPC980/982 timeout values. Table 87. Watchdog Timer Control register (WDCON - address A7h) bit allocation Symbol PRE2 PRE1 PRE0...

  • Page 101: Watchdog Clock Source

    UM10346 NXP Semiconductors LPC980/982 User manual Table 89. Watchdog timeout vales (designer check) …continued PRE2 to PRE0 WDL in Timeout Period Watchdog Clock Source decimal) (in watchdog 25 KHz Watchdog 400 KHz Watchdog 12 MHz CCLK ⁄ clock cycles) CCLK...

  • Page 102: Watchdog Timer In Timer Mode

    UM10346 NXP Semiconductors LPC980/982 User manual Otherwise, the watchdog could become disabled when CCLK turns off. The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first. WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH...

  • Page 103: Power-Down Operation

    UM10346 NXP Semiconductors LPC980/982 User manual WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH 400 kHz PCLK oscillator 8-BIT DOWN ÷32 PRESCALER interrupt 25 kHz COUNTER crystal watchdog oscillator oscillator oscillator XTALWD (CLKCON.4) SHADOW REGISTER WDMOD (CLKCON.5) WDCON (A7H) PRE2...

  • Page 104: Software Reset

    DPTR) will be affected by the setting of DPS. The MOVX instructions have limited application for the P89LPC980/982 since the part does not have an external data bus. However, they may be used to access Flash configuration information (see Flash Configuration section) or auxiliary data (XDATA) memory.

  • Page 105: Flash Memory

    10-year minimum data retention 17.3 Flash programming and erase The P89LPC980/982 program memory consists of four/eight 1 kB sectors. Each sector can be further divided into 64-byte pages. In addition to sector erase and page erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.

  • Page 106: Using Flash As Data Storage: Iap-Lite

    UM10346 NXP Semiconductors LPC980/982 User manual • In-Circuit serial Programming (ICP) with industry-standard commercial programmers. • IAP-Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application. •...
  • Page 107 UM10346 NXP Semiconductors LPC980/982 User manual Writing the erase-program command (68H) to FMCON will start the erase-program process and place the CPU in a program-idle state. The CPU will remain in this idle state until the erase-program cycle is either completed or terminated by an interrupt. When the program-idle state is exited FMCON will contain status information for the cycle.
  • Page 108 UM10346 NXP Semiconductors LPC980/982 User manual Table 94. Flash Memory Control register (FMCON - address E4h) bit description Symbol Access Description Operation interrupted. Set when cycle aborted due to an interrupt or reset. FMCMD.0 W Command byte bit 0. Security violation. Set when an attempt is made to program, erase, or CRC a secured sector or page.

  • Page 109: In-Circuit Programming (Icp)

    The In-Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC980/982 through a two-wire serial interface. NXP has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area.

  • Page 110: Isp And Iap Capabilities Of The P89Lpc980/982

    The P89LPC980/982 contains two special Flash elements: the BOOT VECTOR and the Boot Status Bit. Following reset, the P89LPC980/982 examines the contents of the Boot Status Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code.

  • Page 111: Hardware Activation Of Boot Loader

    The ISP feature requires that an initial character (an uppercase U) be sent to the P89LPC980/982 to establish the baud rate. The ISP firmware provides auto-echo of received characters. Once baud rate initialization has been UM10346_1 ©...
  • Page 112 Should an error occur in the checksum, the P89LPC980/982 will send an ‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed.
  • Page 113 UM10346 NXP Semiconductors LPC980/982 User manual Table 96. In-system Programming (ISP) hex record formats Record type Command/data function Program User Code Memory Page : nnaaaa00dd..ddcc Where: nn = number of bytes to program; aaaa = page address; dd..dd= data bytes;...
  • Page 114 UM10346 NXP Semiconductors LPC980/982 User manual Table 96. In-system Programming (ISP) hex record formats …continued Record type Command/data function Miscellaneous Read Functions : 01xxxx03sscc Where xxxx = required field but value is a ‘don’t care’; ss= subfunction code; cc = checksum...

  • Page 115: In-Application Programming (Iap)

    UM10346 NXP Semiconductors LPC980/982 User manual Table 96. In-system Programming (ISP) hex record formats …continued Record type Command/data function Read Global CRC : 00xxxx06cc Where: xxxx = required field but value is a ‘don’t care’; cc= checksum Example: 00000006FA Direct Load of Baud Rate : 02xxxx07HHLLcc Where: xxxx = required field but value is a ‘don’t care’;...

  • Page 116: Configuration Byte Protection

    UM10346 NXP Semiconductors LPC980/982 User manual is a logic 0, an internal Write Enable (WE) flag is forced set and writes to the flash memory and configuration bytes are enabled. If the Active Write Enable (AWE) bit is a logic 1, then the state of the internal WE flag can be controlled by the user.
  • Page 117 UM10346 NXP Semiconductors LPC980/982 User manual Table 97. IAP error status Flag Description Operation Interrupted. Indicates that an operation was aborted due to an interrupt occurring during a program or erase cycle. Security Violation. Set if program or erase operation fails due to security settings. Cycle is aborted. Memory contents are unchanged.
  • Page 118 UM10346 NXP Semiconductors LPC980/982 User manual Table 98. IAP function calls IAP function IAP call parameters Program User Code Page Input parameters: (requires ‘key’) ACC = 00h R3= number of bytes to program R4= page address (MSB) R5= page address (LSB)
  • Page 119 UM10346 NXP Semiconductors LPC980/982 User manual Table 98. IAP function calls …continued IAP function IAP call parameters Misc. Read Input parameters: ACC = 03h R7= register address 00= UCFG1 01= UCFG2 02= Boot Vector 03= Status Byte 04 to 07 = reserved...

  • Page 120: User Configuration Bytes

    R7= data 17.17 User configuration bytes A number of user-configurable features of the P89LPC980/982 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of an Flash byte UCFG1 and UCFG2 shown in...

  • Page 121: User Security Bytes

    UM10346 NXP Semiconductors LPC980/982 User manual Table 100. Flash User Configuration Byte 1 (UCFG1) bit description …continued Bit Symbol Description BOE0 Brownout Detect Configuration (see Section 5.1 “Brownout detection”) BOE1 BOE2 Reset pin enable. When set = 1, enables the reset function of pin P1.5. When cleared, P1.5 may be used as an input pin.

  • Page 122: Boot Vector Register

    0:4 BOOTV[0:4] Boot vector. If the Boot Vector is selected as the reset address, the P89LPC980/982 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset.
  • Page 123 Bit Symbol Description Boot Status Bit. If programmed to logic 1, the P89LPC980/982 will always start execution at an address comprised of 00H in the lower eight bits and BOOTVEC as the upper bits after a reset. (See Section 6.1 “Reset...

  • Page 124: Instruction Set

    UM10346 NXP Semiconductors LPC980/982 User manual 18. Instruction set Table 111. Instruction set summary Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A,Rn Add register to A 28 to 2F ADD A,dir Add direct byte to A ADD A,@Ri Add indirect memory to A...
  • Page 125 UM10346 NXP Semiconductors LPC980/982 User manual Table 111. Instruction set summary …continued Mnemonic Description Bytes Cycles Hex code XRL A,Rn Exclusive-OR register to A 68 to 6F XRL A,dir Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect memory to A...
  • Page 126 UM10346 NXP Semiconductors LPC980/982 User manual Table 111. Instruction set summary …continued Mnemonic Description Bytes Cycles Hex code XCHD A,@Ri Exchange A and indirect memory nibble D6 to D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry...

  • Page 127: Legal Information

    19.3 Trademarks Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without Notice: All referenced brands, product names, service names and trademarks limitation specifications and product descriptions, at any time and without are the property of their respective owners.

  • Page 128: Tables

    Table 36. Timer/Counter x Control(TxCON - where x = 2, 3 Table 2. Special function registers - P89LPC980/982 . .12 or 4) bit allocation..... . . 47 Table 3.
  • Page 129 UM10346 NXP Semiconductors LPC980/982 User manual description ......83 Table 106.Effects of Security Bits ....122 Table 72.

  • Page 130: Figures

    Fig 3. P89LPC980/982 logic symbol ....9 Fig 49. Forcing ISP mode ..... . . 111 Fig 4.

  • Page 131: Table Of Contents

    UM10346 NXP Semiconductors LPC980/982 User manual 22. Contents Introduction ......3 Mode 2: 16-bit PWM mode ....51 Timer overflow toggle output .
  • Page 132 17.6 ISP and IAP capabilities of the P89LPC980/982 ..... . 110 17.7 Boot ROM ......110 17.8...

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