NXP Semiconductors P89LPC9321 UM10310 User Manual
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NXP Semiconductors P89LPC9321 UM10310 User Manual

NXP Semiconductors P89LPC9321 UM10310 User Manual

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UM10310
P89LPC9321 User manual
Rev. 01 — 1 December 2008
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P89LPC9321
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Technical information for the P89LPC9321 device
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Summary of Contents for NXP Semiconductors P89LPC9321 UM10310

  • Page 1 UM10310 P89LPC9321 User manual Rev. 01 — 1 December 2008 Document information Info Content Keywords P89LPC9321 Abstract Technical information for the P89LPC9321 device User manual...

  • Page 2: Contact Information

    NXP Semiconductors Revision history Date Description 20081201 Initial version. Contact information For more information, please visit: For sales office addresses, please send an email to: UM10310_1 User manual http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 1 December 2008 UM10310 P89LPC9321 User manual ©...

  • Page 3: Introduction

    NXP Semiconductors 1. Introduction The P89LPC9321 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC9321 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9321 in order to reduce component count, board space, and system cost.
  • Page 4 NXP Semiconductors Fig 2. PLCC28 pin configuration Fig 3. DIP28 pin configuration UM10310_1 User manual P1.6/OCB P1.5/RST P3.1/XTAL1 P89LPC9321FA P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA P2.0/ICB P2.1/OCD P0.0/CMP2/KBI0 P1.7/OCC P1.6/OCB P1.5/RST P89LPC9321FN P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL P2.2/MOSI P2.3/MISO 002aae106 Rev. 01 — 1 December 2008...

  • Page 5: Pin Description

    NXP Semiconductors 1.2 Pin description Table 1. Pin description Symbol Type P0.0 to P0.7 P0.0/CMP2/ KBI0 3 P0.1/CIN2B/ KBI1 P0.2/CIN2A/ KBI2 P0.3/CIN1B/ KBI3 P0.4/CIN1A/ KBI4 P0.5/CMPREF/ KBI5 P0.6/CMP1/ KBI6 20 P0.7/T1/KBI7 P1.0 to P1.7 I/O, I UM10310_1 User manual Description Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.
  • Page 6 NXP Semiconductors Table 1. Pin description …continued Symbol Type P1.0/TXD P1.1/RXD P1.2/T0/SCL P1.3/INT0/SDA P1.4/INT1 P1.5/RST P1.6/OCB P1.7/OCC P2.0 to P2.7 P2.0/ICB P2.1/OCD P2.2/MOSI P2.3/MISO P2.4/SS UM10310_1 User manual Description P1.0 — Port 1 bit 0. TXD — Transmitter output for serial port.
  • Page 7 NXP Semiconductors Table 1. Pin description …continued Symbol Type P2.5/SPICLK P2.6/OCA P2.7/ICA P3.0 to P3.1 P3.0/XTAL2/ CLKOUT P3.1/XTAL1 Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. UM10310_1 User manual Description P2.5 — Port 2 bit 5. SPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input.

  • Page 8: Functional Diagram

    NXP Semiconductors 1.3 Functional diagram CLKOUT Fig 4. Functional diagram UM10310_1 User manual KBI0 CMP2 KBI1 CIN2B KBI2 CIN2A KBI3 CIN1B PORT 0 KBI4 CIN1A KBI5 CMPREF KBI6 CMP1 KBI7 P89LPC9321 XTAL2 PORT 3 XTAL1 Rev. 01 — 1 December 2008...

  • Page 9: Block Diagram

    NXP Semiconductors 1.4 Block diagram P89LPC9321 P3[1:0] CONFIGURABLE I/Os P2[7:0] CONFIGURABLE I/Os P1[7:0] CONFIGURABLE I/Os P0[7:0] CONFIGURABLE I/Os WATCHDOG TIMER PROGRAMMABLE OSCILLATOR DIVIDER XTAL1 CRYSTAL RESONATOR XTAL2 Fig 5. Block diagram UM10310_1 User manual ACCELERATED 2-CLOCK 80C51 CPU 8 kB...

  • Page 10: Special Function Registers

    NXP Semiconductors 1.5 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
  • Page 11 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers * indicates SFRs that are bit addressable. Name Description Bit functions and addresses addr. Bit address ACC* Accumulator AUXR1 Auxiliary CLKLP function register Bit address B register BRGR0 Baud rate generator 0...
  • Page 12 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses addr. DEEDAT Data EEPROM data register DEEADR Data EEPROM address register DIVM CPU clock divide-by-M control DPTR...
  • Page 13 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses addr. I2SCLH Serial clock generator/SCL duty cycle register high I2SCLL Serial clock generator/SCL duty cycle register low I2STAT...
  • Page 14 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses addr. KBCON Keypad control register KBMASK Keypad interrupt mask register KBPATN Keypad pattern register OCRAH Output...
  • Page 15 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses addr. Port 1 Bit address Port 2 Bit address Port 3 P0M1 Port 0 output (P0M1.7) mode 1 P0M2...
  • Page 16 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses addr. RTCH RTC register high RTCL RTC register SADDR Serial port address register SADEN Serial port address enable...
  • Page 17 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses addr. Timer 0 high Timer 1 high CCU timer high CDH TICR2 CCU interrupt TOIE2 control register TIFR2...
  • Page 18 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 2. Special function registers …continued * indicates SFRs that are bit addressable. Name Description Bit functions and addresses addr. Watchdog load WFEED1 Watchdog feed 1 WFEED2 Watchdog feed 2 All ports are in input only (high-impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0.
  • Page 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 3. Extended special function registers Name Description Bit functions and addresses addr. BODCFG FFC8H configuration register CLKCON CLOCK Control FFDEH register PGACON1 PGA1 control FFE1H register PGACON1B PGA1 control FFE4H register B PGA1TRIM8X16X PGA1 trim FFE3H 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIM0 8XTRIM3 8XTRIM2 8XTRIM1 8XTRIM0 register...

  • Page 20: Memory Organization

    NXP Semiconductors 1.6 Memory organization read-protected IAP calls only FF00h IAP entry- IDATA routines FFEFh points entry points for: -51 ASM. code -C code ISP CODE 1FFFh (512B) ISP serial loader 1E00h entry points for: SECTOR 7 -UART (auto-baud) 1C00h 1BFFh -I2C, SPI, etc.

  • Page 21: Clocks

    NXP Semiconductors Table 4. Type DATA IDATA XDATA 2. Clocks 2.1 Enhanced CPU The P89LPC9321 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

  • Page 22: Medium Speed Oscillator Option

    NXP Semiconductors 2.3.2 Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration. 2.3.3 High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration.

  • Page 23: Watchdog Oscillator Option

    NXP Semiconductors Table 6. On-chip RC oscillator trim register (TRIM - address 96h) bit description Symbol TRIM.0 TRIM.1 TRIM.2 TRIM.3 TRIM.4 TRIM.5 ENCLK RCCLK 2.6 Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to ±...

  • Page 24: Clock Sources Switch On The Fly

    NXP Semiconductors HIGH FREQUENCY XTAL1 MEDIUM FREQUENCY XTAL2 LOW FREQUENCY RC OSCILLATOR WITH CLOCK DOUBLER (7.3728 MHz/14.7456 MHz ± 1 %) WATCHDOG OSCILLATOR (400 kHz ± 5 %) Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

  • Page 25: Oscillator Clock (Oscclk) Wake-Up Delay

    NXP Semiconductors Table 9. Oscillator type selection for clock switch FOSC[2:0] Oscillator configuration External clock input on XTAL1. Watchdog Oscillator, 400 kHz ± 5 %. Internal RC oscillator, 7.373 MHz ± 1 %. Low frequency crystal, 20 kHz to 100 kHz.

  • Page 26: Interrupt Priority Structure

    NXP Semiconductors Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global enable bit, EA, which enables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H.

  • Page 27: External Interrupt Pin Glitch Suppression

    NXP Semiconductors If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is generated. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.

  • Page 28: I/O Ports

    NXP Semiconductors RTCF ERTC (RTCCON.1) WDOVF any CCU interrupt Fig 9. Interrupt sources, interrupt enables, and power-down wake-up sources. 4. I/O ports The P89LPC9321 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1,and 2 are 8-bit ports, and Port 3 is a 2-bit port.

  • Page 29: Port Configurations

    NXP Semiconductors 4.1 Port configurations All but three I/O port pins on the P89LPC9321 may be configured by software to one of four types on a pin-by-pin basis, as shown in (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin.

  • Page 30: Open Drain Output Configuration

    NXP Semiconductors (Please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter specifications). port latch data Fig 10. Quasi-bidirectional output. 4.3 Open drain output configuration The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic 0.

  • Page 31: Input-Only Configuration

    NXP Semiconductors 4.4 Input-only configuration The input port configuration is shown in has a glitch suppression circuit. (Please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter specifications). Fig 12. Input only. 4.5 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1.

  • Page 32: Additional Port Features

    NXP Semiconductors Digital outputs are disabled by putting the port pins into the input-only mode as described in the Port Configurations section (see Digital inputs on Port 0 may be disabled through the use of the PT0AD register. Bits 1 through 5 in this register correspond to pins P0.1 through P0.5 of Port 0, respectively.

  • Page 33: Power Monitoring Functions

    NXP Semiconductors Table 14. Port pin Configuration SFR bits PxM1.y P2.3 P2M1.3 P2.4 P2M1.4 P2.5 P2M1.5 P2.6 P2M1.6 P2.7 P2M1.7 P3.0 P3M1.0 P3.1 P3M1.1 5. Power monitoring functions The P89LPC9321 incorporates power monitoring functions designed to prevent incorrect operation during initial power-on and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect.

  • Page 34: Power-On Detection

    NXP Semiconductors For correct activation of Brownout Detect, certain V observed. Please see the data sheet for specifications. Table 15. BOE1 (UCFG1.5) Table 16. PMOD1/PMOD0(PCON[1:0]) 11 (total power-down) ≠ 11 (any mode other than total power down) 5.2 Power-on detection...
  • Page 35 NXP Semiconductors Table 17. Power reduction modes PMOD1 PMOD0 Description (PCON.1) (PCON.0) Normal mode (default) - no power reduction. Idle mode. The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.
  • Page 36 NXP Semiconductors Table 18. Power Control register (PCON - address 87h) bit allocation Symbol SMOD1 SMOD0 Reset Table 19. Power Control register (PCON - address 87h) bit description Symbol PMOD0 PMOD1 SMOD0 SMOD1 Table 20. Power Control register A (PCONA - address B5h) bit allocation...

  • Page 37: Reset

    NXP Semiconductors Table 21. Power Control register A (PCONA - address B5h) bit description Symbol VCPD DEEPD RTCPD 6. Reset The P1.5/RST pin can function as either an active low reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5.

  • Page 38: Reset Vector

    NXP Semiconductors software reset SRST (AUXR1.3) Fig 14. Block diagram of reset Table 22. Reset Sources register (RSTSRC - address DFh) bit allocation Symbol BOIF Reset The value shown is for a power-on reset. Other reset sources will set their corresponding bits.

  • Page 39: Timers 0 And 1

    NXP Semiconductors break reset occurs or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the device has been forced into ISP mode. Otherwise, instructions will be fetched from address 0000H. 7. Timers 0 and 1 The P89LPC9321 has two general-purpose counter/timers which are upward compatible with the 80C51 Timer 0 and Timer 1.

  • Page 40: Mode 0

    NXP Semiconductors Table 26. Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit allocation Symbol Reset Table 27. Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit description Bit Symbol Description T0M2 Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the...

  • Page 41: Mode 2

    NXP Semiconductors 7.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.
  • Page 42 NXP Semiconductors Table 29. Timer/Counter Control register (TCON - address 88h) bit description Bit Symbol Description Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by hardware when the interrupt is processed, or by software.

  • Page 43: Timer Overflow Toggle Output

    NXP Semiconductors C/T = 0 PCLK T0 pin C/T = 1 Gate INT0 pin Osc/2 Fig 18. Timer/counter 0 Mode 3 (two 8-bit counters). C/T = 0 PCLK Gate INTn pin Fig 19. Timer/counter 0 or 1 in mode 6 (PWM auto-reload).

  • Page 44: Real-Time Clock Source

    NXP Semiconductors The Real-time Clock is a 23-bit down counter. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL1-2 oscillator. There are five SFRs used for the RTC: RTCCON — Real-time Clock control.

  • Page 45: Changing Rtcs1/Rtcs0

    NXP Semiconductors 8.2 Changing RTCS1/RTCS0 RTCS1/RTCS0 cannot be changed if the RTC is currently enabled (RTCCON.0 = 1). Setting RTCEN and updating RTCS1/RTCS0 may be done in a single write to RTCCON. However, if RTCEN = 1, this bit must first be cleared before updating RTCS1/RTCS0.
  • Page 46 NXP Semiconductors Table 30. FOSC2:0 Table 31. Symbol RTCF Reset UM10310_1 User manual Real-time Clock/System Timer clock sources RCCLK RTCS1:0 RTC clock source Low frequency crystal Low frequency crystal /DIV Low frequency crystal Internal RC oscillator High frequency crystal Medium frequency crystal...

  • Page 47: Capture/Compare Unit (Ccu)

    NXP Semiconductors Table 32. Symbol RTCEN ERTC RTCS0 RTCS1 RTCF 9. Capture/Compare Unit (CCU) This unit features: • A 16-bit timer with 16-bit reload on overflow • Selectable clock (CCUCLK), with a prescaler to divide the clock source by any integer between 1 and 1024.

  • Page 48: Basic Timer Operation

    NXP Semiconductors 16-BIT SHADOW REGISTER TOR2H TO TOR2L 16-BIT TIMER RELOAD REGISTER OVERFLOW/ UNDERFLOW 16-BIT UP/DOWN TIMER WITH RELOAD 10-BIT DIVIDER 4-BIT 32 × PLL DIVIDER Fig 21. Capture Compare Unit block diagram. 9.3 Basic timer operation The Timer is a free-running up/down counter counting at the pace determined by the prescaler.
  • Page 49 NXP Semiconductors depends on whether the timer is running in PWM mode or in basic timer mode. In basic timer mode, writing a one to TCOU2 will cause the values to be latched immediately and the value of TCOU2 will always read as zero. In PWM mode, writing a one to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow.

  • Page 50: Output Compare

    NXP Semiconductors Table 36. Table 37. CCU control register 0 (TCR20 - address C8h) bit allocation Symbol PLLEN HLTRN Reset Table 38. CCU control register 0 (TCR20 - address C8h) bit description Bit Symbol Description 1:2 TMOD20/21 CCU Timer mode (TMOD21, TMOD20): 00 —...

  • Page 51: Input Capture

    NXP Semiconductors In order for a Compare Output Action to occur, the compare values must be within the counting range of the CCU timer. When the compare channel is enabled, the I/O pin (which must be configured as an output) will be connected to an internal latch controlled by the compare logic. The value of this latch is zero from reset and can be changed by invoking a forced compare.

  • Page 52: Pwm Operation

    NXP Semiconductors Input Capture Edge Select - ICESx bit (x being A or B) in the CCCRx register. The user will have to configure the associated I/O pin as an input in order for an external event to trigger a capture.

  • Page 53: Alternating Output Mode

    NXP Semiconductors The user will have to configure the output compare pins as outputs in order to enable the PWM output. As with basic timer operation, when the PWM (compare) pins are connected to the compare logic, their logic state remains unchanged. However, since the bit FCO is used to hold the halt value, only a compare event can change the state of the pin.

  • Page 54: Synchronized Pwm Register Update

    NXP Semiconductors Fig 24. Alternate output mode. Table 42. OCMx1 x = A, B, C, D ‘ON’ means in the CCUCLK cycle after the event takes place. 9.8 Synchronized PWM register update When the OCRx registers are written, a built in mechanism ensures that the value is not updated in the middle of a PWM pulse.

  • Page 55: Pll Operation

    NXP Semiconductors still operate as normal even if it has this added functionality enabled. When the PWM unit is halted, the timer will still run as normal. The HLTRN bit in TCR20 will be set to indicate that a halt took place. In order to re-activate the PWM, the user must clear the HLTRN bit.

  • Page 56: Ccu Interrupt Structure

    NXP Semiconductors • The user is discouraged from writing or reading the timer in asynchronous mode. The results may be unpredictable • Interrupts and flags are asynchronous. There will be delay as the event may not actually be recognized until some CCLK cycles later (for interrupts and reads) 9.11 CCU interrupt structure...
  • Page 57 NXP Semiconductors EA (IEN0.7) ECCU (IEN1.4) TOIE2 (TICR2.7) TOIF2 (TIFR2.7) TICIE2A (TICR2.0) TICF2A (TIFR2.0) TICIE2B (TICR2.1) TICF2B (TIFR2.1) TOCIE2A (TICR2.3) TOCF2A (TIFR2.3) TOCIE2B (TICR2.4) TOCF2B (TIFR2.4) TOCIE2C (TICR2.5) TOCF2C (TIFR2.5) TOCIE2D (TICR2.6) TOCF2D (TIFR2.6) Fig 25. Capture/compare unit interrupts. Table 45.
  • Page 58 NXP Semiconductors Table 47. CCU interrupt flag register (TIFR2 - address E9h) bit allocation Symbol TOIF2 TOCF2D Reset Table 48. CCU interrupt flag register (TIFR2 - address E9h) bit description Bit Symbol Description TICF2A Input Capture Channel A Interrupt Flag Bit. Set by hardware when an input capture event is detected.

  • Page 59: Uart

    NXP Semiconductors Table 50. CCU interrupt control register (TICR2 - address C9h) bit description Bit Symbol Description TOCIE2C Output Compare Channel C Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel C is enabled and the contents of TH2:TL2 match that of OCRHC:OCRLC, the program counter will vectored to the corresponding interrupt.

  • Page 60: Mode 3

    NXP Semiconductors 10.4 Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). Mode 3 is the same as Mode 2 in all respects except baud rate.

  • Page 61: Framing Error

    NXP Semiconductors Table 52. SCON.7 (SM0) Table 53. Symbol Reset Table 54. Bit Symbol BRGEN SBRGS 2:7 - baud rate generator Fig 26. Baud rate generation for UART (Modes 1, 3) 10.8 Framing error A Framing error occurs when the stop bit is sensed as a logic 0. A Framing error is reported in the status register (SSTAT).
  • Page 62 NXP Semiconductors Table 55. Symbol Reset Table 56. Bit Symbol SM0/FE Table 57. SM0, SM1 Table 58. Symbol DBMOD Reset UM10310_1 User manual Serial Port Control register (SCON - address 98h) bit allocation SM0/FE Serial Port Control register (SCON - address 98h) bit description Description Receive interrupt flag.

  • Page 63: More About Uart Mode 0

    NXP Semiconductors Table 59. Bit Symbol STINT DBISEL CIDIS INTLO DBMOD Double buffering mode. When set = 1 enables double buffering. Must be logic 0 for 10.10 More about UART Mode 0 In Mode 0, a write to SBUF will initiate a transmission. At the end of the transmission, TI (SCON.1) is set, which must be cleared in software.

  • Page 64: More About Uart Mode 1

    NXP Semiconductors S1 ... S16 S1 ... S16 S1 ... S16 write to SBUF shift RXD (data out) TXD (shift clock) WRITE to SCON (clear RI) shift (data in) TXD (shift clock) Fig 27. Serial Port Mode 0 (double buffering must be disabled) 10.11 More about UART Mode 1...

  • Page 65: More About Uart Modes 2 And 3

    NXP Semiconductors TX clock write to SBUF shift start clock start ÷16 reset shift Fig 28. Serial Port Mode 1 (only single transmit buffering case is shown) 10.12 More about UART Modes 2 and 3 Reception is the same as in Mode 1.

  • Page 66: Break Detect

    NXP Semiconductors Table 60. Mode PCON.6 (SMOD0) 10.14 Break detect A break is detected when 11 consecutive bits are sensed low and is reported in the status register (SSTAT). For Mode 1, this consists of the start bit, 8 data bits, and two stop bit times.

  • Page 67: The 9Th Bit (Bit 8) In Double Buffering (Modes 1, 2, And 3)

    NXP Semiconductors – If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter (which is also the last data). – If DBISEL is logic 1 and INTLO is logic 1, a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter (which is also the last data).

  • Page 68: Multiprocessor Communications

    NXP Semiconductors If double buffering is enabled, TB8 MUST be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. The operation described in the 10.17 “Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)”...

  • Page 69: Automatic Address Recognition

    NXP Semiconductors 10.20 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port.

  • Page 70: C Interface

    NXP Semiconductors reset SADDR and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well as a Broadcast address of all ‘don’t cares’. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature.

  • Page 71: I 2 C Data Register

    NXP Semiconductors Fig 31. I The P89LPC9321 CPU interfaces with the I (SFRs): I2CON (I Register), I2ADR (I Byte), and I2SCLL (SCL Duty Cycle Register Low Byte). 11.1 I C data register I2DAT register contains the data to be transmitted or the data received. The CPU can read and write to this 8-bit register while it is not in the process of shifting a byte.

  • Page 72: I 2 C Control Register

    NXP Semiconductors 11.3 I C control register The CPU can read and write this register. There are two bits are affected by hardware: the SI bit and the STO bit. The SI bit is set by hardware and the STO bit is cleared by hardware.

  • Page 73: I 2 C Status Register

    NXP Semiconductors Table 67. Bit Symbol I2EN 11.4 I C Status register This is a read-only register. It contains the status code of the I bits are always 0. There are 26 possible status codes. When the code is F8H, there is no relevant information available and SI bit is not set.

  • Page 74: C Operation Modes

    NXP Semiconductors The values for I2SCLL and I2SCLH do not have to be the same; the user can give different duty cycles for SCL by setting these two registers. However, the value of the register must ensure that the data rate is in the I the values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommended.

  • Page 75: Master Receiver Mode

    NXP Semiconductors The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.

  • Page 76: Slave Receiver Mode

    NXP Semiconductors Fig 33. Format of Master Receiver mode. After a repeated START condition, I logic 0 = write logic 1 = read from Master to Slave from Slave to Master Fig 34. A Master Receiver switches to Master Transmitter after sending Repeated Start.

  • Page 77: Slave Transmitter Mode

    NXP Semiconductors Fig 35. Format of Slave Receiver mode. 11.6.4 Slave Transmitter mode The first byte is received and handled as in the Slave Receiver Mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via P1.3/SDA while the serial clock is input through P1.2/SCL.
  • Page 78 NXP Semiconductors P1.3/SDA P1.2/SCL Fig 37. I UM10310_1 User manual ADDRESS REGISTER P1.3 INPUT FILTER OUTPUT STAGE BIT COUNTER / ARBITRATION & INPUT SYNC LOGIC FILTER SERIAL CLOCK OUTPUT GENERATOR STAGE timer 1 overflow I2CON P1.2 I2SCLH SCL DUTY CYCLE REGISTERS...
  • Page 79 NXP Semiconductors Table 73. Master Transmitter mode Status code Status of the I (I2STAT) hardware A START condition has been transmitted A repeat START condition has been transmitted SLA+W has been transmitted; ACK has been received SLA+W has been transmitted;...
  • Page 80 NXP Semiconductors Table 73. Master Transmitter mode Status code Status of the I (I2STAT) hardware Data byte in I2DAT has been transmitted, NOT ACK has been received Arbitration lost in SLA+R/W or data bytes Table 74. Master Receiver mode Status code...
  • Page 81 NXP Semiconductors Table 74. Master Receiver mode …continued Status code Status of the I (I2STAT) hardware Data byte has been received; ACK has been returned Data byte has been received; NACK has been returned Table 75. Slave Receiver mode Status code...
  • Page 82 NXP Semiconductors Table 75. Slave Receiver mode …continued Status code Status of the I (I2STAT) hardware Previously addressed with own SLA address; Data has been received; NACK has been returned Previously addressed with General call; Data has been received; ACK...
  • Page 83 NXP Semiconductors Table 75. Slave Receiver mode …continued Status code Status of the I (I2STAT) hardware A STOP condition or repeated START condition has been received while still addressed as SLA/REC or SLA/TRX Table 76. Slave Transmitter mode Status code...

  • Page 84: Serial Peripheral Interface (Spi)

    NXP Semiconductors Table 76. Slave Transmitter mode Status code Status of the I (I2STAT) hardware Data byte in I2DAT has been transmitted; NACK has been received Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received 12.
  • Page 85 NXP Semiconductors CPU clock DIVIDER BY 4, 16, 64, 128 SPI clock (master) SELECT SPI CONTROL SPI STATUS REGISTER interrupt request Fig 38. SPI block diagram. The SPI interface has four pins: SPICLK, MOSI, MISO and SS: • SPICLK, MOSI and MISO are typically tied together between two or more SPI devices.
  • Page 86 NXP Semiconductors Table 78. Bit Symbol SPR0 SPR1 CPHA CPOL MSTR DORD SPEN SSIG Table 79. Symbol SPIF Reset Table 80. Bit Symbol 0:5 - WCOL SPIF UM10310_1 User manual SPI Control register (SPCTL - address E2h) bit description Description...
  • Page 87 NXP Semiconductors Table 81. Symbol Reset Fig 39. SPI single master single slave configuration. Figure 39, SSIG (SPCTL.7) for the slave is logic 0, and SS is used to select the slave. The SPI master can use any port pin (including P2.4/SS) to drive the SS pin.

  • Page 88: Configuring The Spi

    NXP Semiconductors Fig 41. SPI single master multiple slaves configuration. Figure 41, SSIG (SPCTL.7) bits for the slaves are logic 0, and the slaves are selected by the corresponding SS signals. The SPI master can use any port pin (including P2.4/SS) to drive the SS pins.

  • Page 89: Additional Considerations For A Slave

    NXP Semiconductors Table 82. SPI master and slave selection SPEN SSIG SS Pin MSTR Master or Slave Mode Master (idle) Master (active) P2.4 Slave P2.4 Master Selected as a port function The MSTR bit changes to logic 0 automatically when SS becomes low in input mode and SSIG is logic 0.

  • Page 90: Write Collision

    NXP Semiconductors slave and start sending data to it. To avoid bus contention, the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be an input and MISO becomes an output.
  • Page 91 NXP Semiconductors Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) (1) Not defined Fig 42. SPI slave transfer format with CPHA = 0.
  • Page 92 NXP Semiconductors Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) (1) Not defined Fig 43. SPI slave transfer format with CPHA = 1.
  • Page 93 NXP Semiconductors Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) (1) Not defined Fig 44. SPI master transfer format with CPHA = 0.

  • Page 94: Spi Clock Prescaler Select

    NXP Semiconductors Clock cycle SPICLK (CPOL = 0) SPICLK (CPOL = 1) DORD = 0 MOSI (input) DORD = 1 DORD = 0 MISO (output) DORD = 1 SS (if SSIG bit = 0) (1) Not defined Fig 45. SPI master transfer format with CPHA = 1.
  • Page 95 NXP Semiconductors The overall connections to both comparators are shown in possible configurations for each comparator, as determined by the control bits in the corresponding CMPn register: CPn, CNn, and OEn. These configurations are shown in Figure When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds.

  • Page 96: Internal Reference Voltage

    NXP Semiconductors (P0.4) CIN1A (P0.3) CIN1B PGA1 (P0.5) CMPREF (P0.2) CIN2A (P0.1) CIN2B Fig 46. Comparator input and output connections. 13.2 Internal reference voltage An internal reference voltage, V comparator input pin is used. Please refer to the P89LPC9321 data sheet for specifications.

  • Page 97: Comparators And Power Reduction Modes

    NXP Semiconductors 13.5 Comparators and power reduction modes Either or both comparators may remain enabled when Power-down mode or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor.

  • Page 98: Programmable Gain Amplifier

    NXP Semiconductors pin. CALL delay10us before use. ANL CMP1,#0FEh SETB EC SETB EA The interrupt routine used for the comparator must clear the interrupt flag (CMF1 in this case) before returning. 13.7 Programmable Gain Amplifier (PGA) PGA1 is integrated to amplify the comparators inputs. A single channel can be selected for amplification.
  • Page 99 NXP Semiconductors Table 85. Register bits PGAxTRIM2X4X[3:0] PGAxTRIM2X4X[7:4] PGAxTRIM8X16X[3:0] PGAxTRIM8X16X[7:4] If PGA is enabled, it will consume power. Power can be reduced by disabling the PGA. PGA can be disabled via clearing ENPGAx bit. In Power-down mode or Total Power-down mode, PGA does not function.

  • Page 100: Keypad Interrupt (Kbi)

    NXP Semiconductors 14. Keypad interrupt (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks.

  • Page 101: Watchdog Timer (Wdt)

    NXP Semiconductors Table 94. Keypad Interrupt Mask register (KBMASK - address 86h) bit allocation Symbol KBMASK.7 KBMASK.6 Reset Table 95. Keypad Interrupt Mask register (KBMASK - address 86h) bit description Bit Symbol Description KBMASK.0 When set, enables P0.0 as a cause of a Keypad Interrupt.

  • Page 102: Feed Sequence

    NXP Semiconductors external crystal oscillator or the watchdog oscillator selected by the WDCLK bit in the WDCON register and XTALWD bit in the CLKCON register. (Note that switching of the clock sources will not take effect immediately - see The watchdog asserts the watchdog reset when the watchdog count underflows and the watchdog reset is enabled.
  • Page 103 NXP Semiconductors To feed the watchdog, two write instructions must be sequentially executed successfully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register.
  • Page 104 NXP Semiconductors tclks Table 99 shows sample P89LPC9321 timeout values. Table 97. Watchdog Timer Control register (WDCON - address A7h) bit allocation Symbol PRE2 PRE1 Reset Table 98. Watchdog Timer Control register (WDCON - address A7h) bit description Bit Symbol...

  • Page 105: Watchdog Clock Source

    NXP Semiconductors 15.3 Watchdog clock source The watchdog timer system has an on-chip 400 KHz oscillator. The watchdog timer can be clocked from the watchdog oscillator, PCLK or external crystal oscillator (refer to Figure 49) by configuring the WDCLK bit in the Watchdog Control Register WDCON and XTALWD bit in CLKCON register.

  • Page 106: Watchdog Timer In Timer Mode

    NXP Semiconductors MOV WFEED1, #0A5H MOV WFEED2, #05AH PCLK Watchdog ÷32 oscillator external crystal oscillator XTALWD WDCON (A7H) Fig 50. Watchdog Timer in Watchdog Mode (WDTE = 1). 15.4 Watchdog Timer in Timer mode Figure 51 shows the Watchdog Timer in Timer Mode. In this mode, any changes to WDCON are written to the shadow register after one watchdog clock cycle.

  • Page 107: Power-Down Operation

    NXP Semiconductors MOV WFEED1, #0A5H MOV WFEED2, #05AH PCLK Watchdog ÷32 oscillator external crystal oscillator XTALWD WDCON (A7H) Fig 51. Watchdog Timer in Timer Mode (WDTE = 0). 15.5 Power-down operation The WDT oscillator and external crystal oscillator will continue to run in power-down, consuming approximately 50 μA, as long as the WDT oscillator is selected as the clock...

  • Page 108: Software Reset

    NXP Semiconductors Table 102. AUXR1 register (address A2h) bit description Bit Symbol SRST ENT0 ENT1 EBRR CLKLP 16.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. If a value is written to AUXR1 that contains a 1 at bit position 3, all SFRs will be initialized and execution will resume at program address 0000.

  • Page 109: Data Eeprom

    NXP Semiconductors Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.

  • Page 110: Data Eeprom Read

    NXP Semiconductors Row Fill: In this mode the addressed row (64 bytes, with address DEEADR[5:0] ignored) is filled with the DEEDAT pattern. To erase the entire row to 00h or program the entire row to FFh, write 00h or FFh to DEEDAT prior to row fill. Each row fill requires approximately 4 ms to complete.

  • Page 111: Hardware Reset

    NXP Semiconductors 5. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are logic 1s, wait for the Data EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF is logic 1, the operation is complete and data is written.

  • Page 112: Data Eeprom Block Fill

    NXP Semiconductors 5. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are logic 1s, wait for the Data EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF is logic 1, the operation is complete and row is filled with the DEEDAT pattern.

  • Page 113: Flash Programming And Erase

    NXP Semiconductors • Internal fixed boot ROM, containing low-level In-Application Programming (IAP) routines that can be called from the end application (in addition to IAP-Lite). • Default serial loader providing In-System Programming (ISP) via the serial port, located in upper end of user program memory.
  • Page 114 NXP Semiconductors • FMDATA (Flash Data Register). Accepts data to be loaded into the page register. The page register consists of 64 bytes and an update flag for each byte. When a LOAD command is issued to FMCON the page register contents and all of the update flags will be cleared.
  • Page 115 NXP Semiconductors • Write the data for the next byte to be programmed to FMDATA. • Repeat writing of FMADRL and/or FMDATA until all desired bytes have been loaded into the page register. • Write the page address in user code memory to FMADRH and FMADRL[7:6], if not previously included when writing the page register address to FMADRL[5:0].
  • Page 116 NXP Semiconductors ;* C = clear on no error, set on error ;************************************************** LOAD PGM_USER: LOAD_PAGE: BAD: A C-language routine to load the page register and perform an erase/program operation is shown below. #include <REG9351.H> unsigned char idata dbytes[64]; // data buffer unsigned char Fm_stat;...

  • Page 117: In-Circuit Programming (Icp)

    NXP Semiconductors 18.5 In-circuit programming (ICP) In-Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system. The In-Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC9321 through a two-wire serial interface.

  • Page 118: Hardware Activation Of Boot Loader

    NXP Semiconductors The factory default settings for this device is shown in The factory pre-programmed boot loader can be erased by the user. Users who wish to use this loader should take cautions to avoid erasing the last 1 kB sector on the device.

  • Page 119: Using The In-System Programming (Isp)

    NXP Semiconductors expense in components and circuit board area. The ISP function uses five pins (V TXD0, RXD0, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.
  • Page 120 NXP Semiconductors Table 108. In-system Programming (ISP) hex record formats Record type UM10310_1 User manual Command/data function Program User Code Memory Page : nnaaaa00dd..ddcc Where: nn = number of bytes to program; aaaa = page address; dd..dd= data bytes; cc = checksum;...
  • Page 121 NXP Semiconductors Table 108. In-system Programming (ISP) hex record formats Record type UM10310_1 User manual Command/data function Miscellaneous Read Functions : 01xxxx03sscc Where xxxx = required field but value is a ‘don’t care’; ss= subfunction code; cc = checksum Subfunction codes:...

  • Page 122: In-Application Programming (Iap)

    NXP Semiconductors Table 108. In-system Programming (ISP) hex record formats Record type 18.12 In-application programming (IAP) Several In-Application Programming (IAP) calls are available for use by an application program to permit selective erasing and programming of Flash sectors, pages, security bits, configuration bytes, and device id.

  • Page 123: Configuration Byte Protection

    NXP Semiconductors is a logic 0, an internal Write Enable (WE) flag is forced set and writes to the flash memory and configuration bytes are enabled. If the Active Write Enable (AWE) bit is a logic 1, then the state of the internal WE flag can be controlled by the user.
  • Page 124 NXP Semiconductors Table 109. IAP error status Flag Description Operation Interrupted. Indicates that an operation was aborted due to an interrupt occurring during a program or erase cycle. Security Violation. Set if program or erase operation fails due to security settings. Cycle is aborted. Memory contents are unchanged.
  • Page 125 NXP Semiconductors Table 110. IAP function calls IAP function Program User Code Page (requires ‘key’) Read Version Id Misc. Write (requires ‘key’) Input parameters: UM10310_1 User manual IAP call parameters Input parameters: ACC = 00h R3= number of bytes to program...
  • Page 126 NXP Semiconductors Table 110. IAP function calls IAP function Misc. Read Erase Sector/Page (requires ‘key’) UM10310_1 User manual …continued IAP call parameters Input parameters: ACC = 03h R7= register address 00= UCFG1 01= UCFG2 02= Boot Vector 03= Status Byte...

  • Page 127: User Configuration Bytes

    NXP Semiconductors Table 110. IAP function calls IAP function Read Sector CRC Read Global CRC Read User Code 18.17 User configuration bytes A number of user-configurable features of the P89LPC9321 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are...

  • Page 128: User Security Bytes

    NXP Semiconductors Table 112. Flash User Configuration Byte 1 (UCFG1) bit description Bit Symbol Description WDSE Watchdog Safety Enable bit. Refer to BOE1 Brownout Detect Configuration (see Reset pin enable. When set = 1, enables the reset function of pin P1.5. When cleared, P1.5 may be used as an input pin.

  • Page 129: Boot Vector Register

    NXP Semiconductors Table 117. Sector Security Bytes (SECx) bit description Bit Symbol Description MOVCDISx MOVC Disable. Disables the MOVC command for sector x. Any MOVC that attempts to read a byte in a MOVC protected sector will return invalid data. This bit can only be erased when sector x is erased.
  • Page 130 NXP Semiconductors Table 122. Boot Status (BOOTSTAT) bit description Bit Symbol Description Boot Status Bit. If programmed to logic 1, the P89LPC9321 will always start execution at an address comprised of 00H in the lower eight bits and BOOTVEC as the upper bits after a reset. (See “Reset...

  • Page 131: Instruction Set

    NXP Semiconductors 19. Instruction set Table 123. Instruction set summary Mnemonic ADD A,Rn ADD A,dir ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,dir ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,dir SUBB A,@Ri SUBB A,#data INC A INC Rn INC dir...
  • Page 132 NXP Semiconductors Table 123. Instruction set summary Mnemonic XRL A,Rn XRL A,dir XRL A, @Ri XRL A,#data XRL dir,A XRL dir,#data CLR A CPL A SWAP A RL A RLC A Rotate A right RRC A MOV A,Rn MOV A,dir...
  • Page 133 NXP Semiconductors Table 123. Instruction set summary Mnemonic XCHD A,@Ri Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C ACALL addr 11 LCALL addr 16...

  • Page 134: Legal Information

    Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice.

  • Page 135: Tables

    NXP Semiconductors 21. Tables Table 1. Pin description ......5 Table 2. Special function registers ....11 Table 3.
  • Page 136 NXP Semiconductors Table 68. I C Status register (I2STAT - address D9h) bit allocation ......73 Table 69.

  • Page 137: Figures

    NXP Semiconductors 22. Figures Fig 1. TSSOP28 pin configuration ....3 Fig 2. PLCC28 pin configuration ....4 Fig 3.

  • Page 138: Table Of Contents

    NXP Semiconductors 23. Contents Introduction ......3 Pin configuration ......3 Pin description .
  • Page 139 NXP Semiconductors 12.7 SPI clock prescaler select ....94 Analog comparators ....94 13.1...

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