NXP Semiconductors LPC5411 Series Product Data Sheet

NXP Semiconductors LPC5411 Series Product Data Sheet

32-bit arm cortex-m4/m0+ mcu; 192 kb sram; 256 kb flash, crystal-less usb operation, dmic subsystem, flexcomm interface, 32-bit counter/ timers, sctimer/pwm, 12-bit 5.0 msamples/sec adc, temperature sensor
Table of Contents

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1. General description

The LPC5411x are ARM Cortex-M4 based microcontrollers for embedded applications.
These devices include an ARM Cortex-M0+ coprocessor, up to 192 KB of on-chip SRAM,
up to 256 KB on-chip flash, full-speed USB device interface with Crystal-less operation, a
DMIC subsystem with PDM microphone interface and I2S, five general-purpose timers,
one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a
Windowed Watchdog Timer (WWDT), eight flexible serial communication peripherals
(each of which can be a USART, SPI, or I
ADC, and a temperature sensor.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point unit is integrated in the core.
The ARM Cortex-M0+ coprocessor is an energy-efficient and easy-to-use 32-bit core
which is code and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor
offers up to 100 MHz performance with a simple instruction set and reduced code size.

2. Features and benefits

LPC5411x
32-bit ARM Cortex-M4/M0+ MCU; 192 KB SRAM; 256 KB flash,
Crystal-less USB operation, DMIC subsystem, Flexcomm
Interface, 32-bit counter/ timers, SCTimer/PWM, 12-bit 5.0
Msamples/sec ADC, Temperature sensor
Rev. 2.1 — 9 May 2018
Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. Both cores operate up
to a maximum frequency of 100 MHz.
ARM Cortex-M4 core (version r0p1):
ARM Cortex-M4 processor, running at a frequency of up to 100 MHz.
Floating Point Unit (FPU) and Memory Protection Unit (MPU).
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,
and four watch points. Includes Serial Wire Output for enhanced debug
capabilities.
System tick timer.
2
C interface), and one 12-bit 5.0 Msamples/sec
Product data sheet

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Summary of Contents for NXP Semiconductors LPC5411 Series

  • Page 1: General Description

    LPC5411x 32-bit ARM Cortex-M4/M0+ MCU; 192 KB SRAM; 256 KB flash, Crystal-less USB operation, DMIC subsystem, Flexcomm Interface, 32-bit counter/ timers, SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC, Temperature sensor Rev. 2.1 — 9 May 2018 Product data sheet 1. General description The LPC5411x are ARM Cortex-M4 based microcontrollers for embedded applications.
  • Page 2: Lpc5411X

    (AND/OR) combination of input states. CRC engine.  LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 2 of 105...
  • Page 3: Lpc5411X

    Wake-up from deep-sleep modes due to activity on the USART, SPI, and I2C peripherals when operating as slaves. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 3 of 105...
  • Page 4: Lpc5411X

      Available as WLCSP49 and LQFP64 packages. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 4 of 105...
  • Page 5: Ordering Information

    LQFP64 package marking Fig 2. WLCSP49 package marking LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 5 of 105...
  • Page 6: Lpc5411X

    Initial device revision with boot code version 18.0. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 6 of 105...
  • Page 7: Block Diagram

    Grey-shaded blocks indicate peripherals that provide DMA requests or are otherwise able to trigger DMA transfers Fig 3. LPC5411x Block diagram LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 7 of 105...
  • Page 8: Pinning Information

    Fig 4. WLCSP49 Pin configuration LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 8 of 105...
  • Page 9: Table Of Contents

    17 PIO1_3 aaa-019386 Fig 5. LQFP64 Pin configuration LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 9 of 105...
  • Page 10: Pin Description

    FC3_SSEL2 — Flexcomm Interface 3: SPI SSEL2. CTimer0_CAP2 — 32-bit CTimer0 capture input 2. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 10 of 105...
  • Page 11: Lpc5411X

    SCT0_OUT3 — SCT0 output 3. PWM output 3. CTimer3_MAT0 — 32-bit CTimer3 match output 0. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 11 of 105...
  • Page 12: Lpc5411X

    FC4_SCK — Flexcomm Interface 4: USART or SPI clock. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 12 of 105...
  • Page 13: Lpc5411X

    FC0_TXD_SCL_MISO — Flexcomm Interface 0: USART TXD, I2C SCL, SPI MISO. CTimer3_MAT0 — 32-bit CTimer3 match output 0. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 13 of 105...
  • Page 14: Lpc5411X

    R — Reserved. CTimer0_CAP3 — 32-bit CTimer0 capture input 3. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 14 of 105...
  • Page 15: Lpc5411X

    R — Reserved. CTimer0_CAP0 — 32-bit CTimer0 capture input 0. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 15 of 105...
  • Page 16: Lpc5411X

    FC3_TXD_SCL_MISO — Flexcomm Interface 3: USART TXD, I2C SCL, SPI MISO. CTimer0_MAT1 — 32-bit CTimer0 match output 1. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 16 of 105...
  • Page 17: Lpc5411X

    R — Reserved. CTimer1_CAP3 — 32-bit CTimer1 capture input 3. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 17 of 105...
  • Page 18: Lpc5411X

    FC7_SCK — Flexcomm Interface 7: USART, SPI, or I2S clock. UTICK_CAP2 — Micro-tick timer capture input 2. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 18 of 105...
  • Page 19: Lpc5411X

    RTC oscillator output. VREFP ADC positive reference voltage. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 19 of 105...
  • Page 20: Lpc5411X

    20 ns (simulated value) 5 V tolerant transparent analog pad. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 20 of 105...
  • Page 21: Termination Of Unused Pins

    Default and programmed pin states are retained in sleep and deep-sleep modes. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 22: Functional Description

    LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 22 of 105...
  • Page 23: Nested Vectored Interrupt Controller (Nvic) For Cortex-M4

    Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 23 of 105...
  • Page 24: System Tick Timer (Systick)

    • • Legacy, Single, and Dual image boot. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 24 of 105...
  • Page 25: Memory Mapping

    LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 25 of 105...
  • Page 26: Lpc5411X

    Table 1 on page 5. Fig 6. LPC5411x Memory mapping LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 26 of 105...
  • Page 27: System Control

    6 kHz to 1.5 MHz. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 28: Clock Input

    LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 28 of 105...
  • Page 29: Lpc5411X

    FRGCLKSEL[2:0] FXCOMCLKSEL[n][2:0] aaa-022102 Fig 8. LPC5411x clock generation LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 29 of 105...
  • Page 30: Brownout Detection

    ISP command to enable a flash update via USART. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 30 of 105...
  • Page 31: Power Control

    RESET pin and the RTC alarm. The ALARM1HZ flag in RTC control register LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 32: Lpc5411X

    HWWAKE Certain Flexcomm Interface and DMIC subsystem activity. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 32 of 105...
  • Page 33: Lpc5411X

    Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC. Reset pin Always available. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 33 of 105...
  • Page 34: General Purpose I/O (Gpio)

    The registers that control the pin interrupt or pattern match engine are located on the I/O+ bus for fast single-cycle access. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 34 of 105...
  • Page 35: Features

    Address increment options allow packing and/or unpacking data. • LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 35 of 105...
  • Page 36: Digital Serial Peripherals

    Data can be streamed directly to I S on Flexcomm Interface 7. • LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 36 of 105...
  • Page 37: Flexcomm Interface Serial Communication

    USART transmit and receive functions work with the system DMA controller. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 38: Spi Serial I/O Controller

    Separate DMA requests for Master, Slave, and Monitor functions. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 38 of 105...
  • Page 39: S-Bus Interface

    Remark: The Flexcomm Interface function clock frequency should not be above 48 MHz. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 40: Standard Counter/Timers (Ctimer0 To 4)

    SCTimer/PWM inputs or outputs, the direction of count, and other factors. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 40 of 105...
  • Page 41: Features

    – Counter value can be loaded into capture register triggered by a match or input/output toggle. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 41 of 105...
  • Page 42: Windowed Watchdog Timer (Wwdt)

    “warning interrupt” time is reached. Flag to indicate Watchdog reset. • LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 42 of 105...
  • Page 43: Rtc Timer

    Repeat interrupt, one-shot interrupt, and one-shot bus stall modes. • LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 43 of 105...
  • Page 44: Micro-Tick Timer (Utick)

    LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 44 of 105...
  • Page 45: Emulation And Debugging

    The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the SWD functions by default. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 45 of 105...
  • Page 46: Limiting Values

    Including the voltage on outputs in 3-state mode. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 46 of 105...
  • Page 47: Thermal Characteristics

    0.3  15 % C/W thermal resistance from th(j-c) junction to case LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 47 of 105...
  • Page 48: Static Characteristics

    Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 49: Coremark Data

    SRAM1 and SRAM2 powered down. SRAM0 and SRAMX powered. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 49 of 105...
  • Page 50: Lpc5411X

    24 MHz, 36 MHz, 60 MHz, 72 MHz, 84 MHz, and 100 MHz: FRO enabled; PLL enabled. Fig 9. Typical CoreMark score LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 50 of 105...
  • Page 51: Power Consumption

    Flash is powered down; SRAM0 and SRAMX are powered; SRAM1 and SRAM2 are powered down. All peripheral clocks disabled. Characterized using low power regulation mode. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 51 of 105...
  • Page 52: Lpc5411X

    Clock source FRO. PLL disabled. All SRAM powered. Compiler settings: Keil µVision 5.17., optimization level 0, optimized for time off. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 53: Lpc5411X

    Guaranteed by characterization, not tested in production. V = 2.0 V. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 53 of 105...
  • Page 54: Lpc5411X

    Fig 11. Deep-sleep mode: Typical supply current I versus temperature for different supply voltages V LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 54 of 105...
  • Page 55: Lpc5411X

    0.43 0.50 0.54 0.54 MAILBOX 0.12 0.12 0.12 LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 55 of 105...
  • Page 56: Lpc5411X

    Typical ratings are not guaranteed. Characterized through bench measurements using typical samples. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 57: Pin Characteristics

     3.6 V drive HIGH; connected to ground; LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 57 of 105...
  • Page 58: Lpc5411X

    HIGH; pad connected to output current ground LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 58 of 105...
  • Page 59: Lpc5411X

    PIO0_n aaa-010819 Fig 13. Pin input/output current measurement LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 59 of 105...
  • Page 60: Electrical Pin Characteristics

    Fig 15. Typical LOW-level output current I versus LOW-level output voltage V LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 60 of 105...
  • Page 61: Lpc5411X

    Fig 17. Typical pull-up current I versus input voltage V LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 61 of 105...
  • Page 62: Lpc5411X

    Fig 18. Typical pull-down current I versus input voltage V LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 62 of 105...
  • Page 63: Dynamic Characteristics

    Simulated data. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 63 of 105...
  • Page 64: Wake-Up Process

    GPIO output pin is set in the reset handler. FRO disabled. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 64 of 105...
  • Page 65: System Pll

    PLL current measured using lowest CCO frequency to obtain the desired output frequency. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 66: Fro

    Parameters are valid over operating temperature range unless otherwise specified. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 66 of 105...
  • Page 67: Watchdog Oscillator

    = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 68: S-Bus Interface

    CCLK = 96 MHz /2) -1 - /2) +1 ns LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 68 of 105...
  • Page 69: Lpc5411X

    CCLK = 48 MHz to 60 MHz CCLK = 96 MHz LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 69 of 105...
  • Page 70: Lpc5411X

    CCLK = 96 MHz Based on characterization; not tested in production. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 70 of 105...
  • Page 71: Lpc5411X

    Fig 21. I S-bus timing (slave) LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 71 of 105...
  • Page 72: Spi Interfaces

    CCLK = 48 MHz to 60 MHz CCLK = 96 MHz LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 72 of 105...
  • Page 73: Lpc5411X

    DATA VALID aaa-014969 Fig 22. SPI master timing LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 73 of 105...
  • Page 74: Lpc5411X

    DATA VALID IDLE aaa-014970 Fig 23. SPI slave timing LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 74 of 105...
  • Page 75: Usart Interface

    CCLK = 48 MHz to 60 MHz CCLK = 96 MHz LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 75 of 105...
  • Page 76: Sctimer/Pwm Output Timing

    Symbol Parameter Conditions Unit output skew time sk(o) LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 76 of 105...
  • Page 77: Dmic Subsystem

    EOPR2 EOP; see Figure 26 LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 77 of 105...
  • Page 78: Lpc5411X

    Fig 26. Differential data-to-EOP transition skew and EOP width LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 78 of 105...
  • Page 79: Analog Characteristics

    3.09 reset level 3 assertion 2.21 de-assertion 2.36 LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 79 of 105...
  • Page 80: 12-Bit Adc Characteristics

    See Figure LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 80 of 105...
  • Page 81: Lpc5411X

    (5) Center of a step of the actual transfer curve. Fig 27. 12-bit ADC characteristics LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 81 of 105...
  • Page 82: Lpc5411X

    < 1 kΩ 1 kΩ  Z < 5 kΩ LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 82 of 105...
  • Page 83: Adc Input Impedance

    C • Table 37 for C • LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 83 of 105...
  • Page 84: Temperature Sensor

    Absolute temperature accuracy. Based on simulation. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 84 of 105...
  • Page 85: Lpc5411X

    Fig 29. LLS fit of the temperature sensor output voltage LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 85 of 105...
  • Page 86: Application Information

    Digital input: Pull-up enabled/disabled. • Digital input: Pull-down enabled/disabled. • LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 86 of 105...
  • Page 87: Lpc5411X

    Fig 31. Standard I/O and RESET pin configuration LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 87 of 105...
  • Page 88: Connecting Power, Clocks, And Debug Functions

    Fig 32. Power, clock, and debug connections LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 88 of 105...
  • Page 89: I/O Power Consumption

    Table 20 for the internal I/O capacitance): x (C LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 89 of 105...
  • Page 90: Rtc Oscillator

    GPIOs and optimize the values of external load capacitors for minimum frequency deviation. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 90 of 105...
  • Page 91: Rtc Printed Circuit Board (Pcb) Design Guidelines

    3.6 V/5.25 V or ~0.686 V. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 92: Lpc5411X

    Fig 35. USB interface on a bus-powered device LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 92 of 105...
  • Page 93: Package Outline

    - - - 16-01-20 Fig 36. WLCSP49 Package outline LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 93 of 105...
  • Page 94: Lpc5411X

    136E10 MS-026 03-02-25 Fig 37. LQFP64 Package outline LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 94 of 105...
  • Page 95: Soldering

    32-bit ARM Cortex-M4/M0+ microcontroller 15. Soldering Fig 38. WLCSP49 Soldering footprint LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 95 of 105...
  • Page 96: Lpc5411X

    0.400 10.500 10.500 13.550 13.550 sot314-2_fr Fig 39. LQFP64 Soldering footprint LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 96 of 105...
  • Page 97: Abbreviations

    17. References Technical note ADC design guidelines: https://www.nxp.com/docs/en/supporting-information/TN00009.pdf LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 97 of 105...
  • Page 98: Revision History

    LPC5411x v.1.6 20161222 Product data sheet LPC5411x v.1.5 LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 98 of 105...
  • Page 99: Lpc5411X

    IDD typical values at deep-sleep mode, flash is powered down. LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018...
  • Page 100: Lpc5411X

    – removed rise time (t ) and fall time (t LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 100 of 105...
  • Page 101: Lpc5411X

    79. LPC5411x v.1 20160216 Product data sheet LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 101 of 105...
  • Page 102: Legal Information

    For detailed and full information see the relevant full data specified use without further testing or modification. sheet, which is available on request via the local NXP Semiconductors sales Customers are responsible for the design and operation of their applications office.
  • Page 103: Trademarks

    NXP Semiconductors’ specifications such use shall be solely at customer’s may be subject to export control regulations. Export might require a prior own risk, and (c) customer fully indemnifies NXP Semiconductors for any authorization from competent authorities. liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’...
  • Page 104: Contents

    General Purpose I/O (GPIO) ... . . 34 continued >> LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2.1 — 9 May 2018 104 of 105...
  • Page 105: Lpc5411X

    Contents ......104 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com...

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