NXP Semiconductors PN7462 series User Manual page 44

Table of Contents

Advertisement

NXP Semiconductors
Voltage Monitor
VBUS2
VBUSP
6.6.1 VBUS monitor
The PN7462 family offers two selectable thresholds (2.3 V or 2.7 V) for monitoring the
voltage on the VBUS pin. When VBUS voltage falls below the selected threshold and
Auto Hard Power Down (HPD) feature is enabled in the Power, Clock and Reset unit
(described in
monitor the signal by reading a dedicated status register and decide to put the IC into the
HPD mode. The signal can be enabled for interrupt in Interrupt Enable register in the
PCR to cause a CPU interrupt. By default, the VBUS monitor is disabled during the
power-up.
6.6.2 PVDD LDO (VBUS2) monitor
The PN7462 family offers two selectable thresholds (VBUS2: 2.7 V or 4.0 V) for
monitoring the voltage of the PVDD LDO supply. The status of the VBUS2 monitor is
available in the status register. The software has to check whether the voltage is
sufficient before enabling the LDO. The PVDD LDO can be enabled when the input
supply VBUS2 > 4.0 V.
6.6.3 VBUSP monitor
VBUSP monitor is used for the Contact interface supply. Three levels (2.7, 3.0, and 3.9
V) can be selected for monitoring the voltage on the VBUSP pin. The threshold is
configured by firmware depending on the card type selected. (Class A, Class B, Class C)
When VBUSP < 2.7 V, no functionality is possible.
When VBUSP > 2.7 V, Class C type can be supported.
When VBUSP > 3.0 V, Class A type can be supported with DC-to-DC converter
configured in the doubler mode.
When VBUSP > 2.7 V and VBUSP < 3.9 V, Class B type is supported with DC-to-DC
converter configured in the doubler mode.
When VBUSP > 3.9 V, Class B type of card is supported with DC-to-DC converter
configured in the follower mode.
When the voltage falls below the selected threshold value and CT automatic deactivation
is enabled in the PCR System Register, the hardware automatically de-activates the CT
interface. The signal can be enabled for interrupt in Interrupt Enable register in the PCR
to cause a CPU interrupt. The software must check VBUSP monitor levels by reading
dedicated status registers before starting card activation sequence.
UM10858
User manual
COMPANY PUBLIC
Threshold 1
2.7 V
2.7 V
Section
0), the IC will enter the HPD mode. Alternatively, the software can
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Threshold 2
Threshold 3
4 V
N/A
3 V
3.9 V
UM10858
© NXP B.V. 2018. All rights reserved.
44 of 345

Advertisement

Table of Contents
loading

Table of Contents