NXP Semiconductors PN7462 series User Manual page 312

NXP Semiconductors
Bit
15
14:11
10:7
6
5
4
3:0
HOSTIF_INT_SET_STATUS_REG
This register is a collection of Set Interrupt Status commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 353. HOSTIF_INT_SET_STATUS_REG (address offset 0x3FEC)
Bit
31:27
UM10858
User manual
COMPANY PUBLIC
Symbol Access
TX_TIMEOUT_CLR_S W
TATUS
RX_FRAME_OVERFL W
OW_CLR_STATUS
RX_FRAME_UNDERF W
LOW_CLR_STATUS
TX_FRAME_NOT_AVAI W
LABLE_CLR_STATUS
RX_BUFFER_NOT_A W
VAILABLE_CLR_STAT
US
EOT_CLR_STATUS W
EOR_CLR_STATUS W
Symbol Access
RESERVED W
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Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset Description
Value
0 1 - clear inter-character timeout (TIC)
exceeded on transmitted frame interrupt
0 - no effect
0 0001 - clear frame overflow interrupt for
RX buffer 0
0010 - clear frame overflow interrupt for
RX buffer 1
0100 - clear frame overflow interrupt for
RX buffer 2
1000 - clear frame overflow interrupt for
RX buffer 3
0000 - no effect
0 0001 - clear frame underflow interrupt for
RX buffer 0
0010 - clear frame underflow interrupt for
RX buffer 1
0100 - clear frame underflow interrupt for
RX buffer 2
1000 - clear frame underflow interrupt for
RX buffer 3
0000 - no effect
0 1 - clear TX frame not available interrupt
0 - no effect
0 1 - clear no receive buffers available
interrupt
0 - no effect
0 1 - clear EOT interrupt
0 - no effect
0 0001 - clear EOR interrupt for RX buffer 0
0010 - clear EOR interrupt for RX buffer 1
0100 - clear EOR interrupt for RX buffer 2
1000 - clear EOR interrupt for RX buffer 3
0000 - no effect
Reset Description
Value
0 Reserved
UM10858
© NXP B.V. 2018. All rights reserved.
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