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NXP Semiconductors
Bit
Symbol
17:16 INTERNAL_USE
[1]
15:14 RESERVED
13:12 INTERNAL_USE
[1]
11
RESERVED
10:8
INTERNAL_USE
[1]
7
RESERVED
6:4
INTERNAL_USE
[1]
3:2
RESERVED
1:0
RESERVED
[1]
Bit-field are either set by HAL or use default value from CLIF EEPROM default settings
Table 237. CLIF_INT_CLR_ENABLE_REG register (address 3FD8h)
* = reset value
Bit
Symbol
31:30
RESERVED
AGC_RFOFF_DET_
29
IRQ_CLR_ENABLE
28
TX_DATA_REQ_IRQ_CLR_E
NABLE
27
RX_DATA_AV_IRQ_CLR_EN
ABLE
26
RX_BUFFER_OVERFLOW_I
RQ_CLR_ENABLE
25
TX_WATERLEVEL_IRQ_CLR
_ENABLE
24
RX_WATERLEVEL_IRQ_CLR
_ENABLE
23
RESERVED
UM10858
User manual
COMPANY PUBLIC
Access
Value
Description
0*-3h
For internal use
R/W
0*
Proportional: 2^(-3) and Integral: 2^(-20)
1
Proportional: 2^(-4) and Integral: 2^(-21)
2
Proportional: 2^(-5) and Integral: 2^(-22)
3
Proportional: 2^(-6) and Integral: 2^(-23)
0
Reserved
R
0*-3h
For internal use
R/W
0*
~37.8 us
1
~75.5 us
2
~151 us
3
~300 us
0
Reserved
R
0*-7h
For internal use
R/W
0*
2^(-10)
7
2^(-17)
0
Reserved
R
0*-7h
For internal use
R/W
0*
2^(-3)
7
2^(-10)
0
Reserved
R
0*-3h
Reserved
R/W
Access
Value
Description
W
0
Reserved
Writing 1 to this register does clear the corresponding IRQ
W
0, 1
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W
0
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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